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--##############################################################################
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--##############################################################################
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-- ION MIPS-compatible CPU demo on Terasic DE-1 Cyclone-II starter board
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-- ION MIPS-compatible CPU demo on Terasic DE-1 Cyclone-II starter board
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--##############################################################################
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--##############################################################################
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-- This module is little more than a wrapper around the CPU and its memories.
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-- This module is little more than a wrapper around the SoC.
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-- Synthesize with 'balanced' optimization for best results.
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-- Synthesize with 'speed' optimization for best results.
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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-- NOTE: See note at bottom of file about optional use of PLL.
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-- NOTE: See note at bottom of file about optional use of PLL.
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--##############################################################################
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--##############################################################################
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-- Copyright (C) 2011 Jose A. Ruiz
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-- Copyright (C) 2011 Jose A. Ruiz
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--
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--
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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use work.mips_pkg.all; -- Only needed if port debug_info is not OPEN
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use work.mips_pkg.all; -- Only needed if port debug_info is not OPEN
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use work.obj_code_pkg.all;
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-- FPGA i/o for Terasic DE-1 board
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-- FPGA i/o for Terasic DE-1 board
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-- (Many of the board's i/o devices will go unused in this demo)
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-- (Many of the board's i/o devices will go unused in this demo)
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entity c2sb_demo is
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entity c2sb_demo is
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port (
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port (
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end function nibble_to_7seg;
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end function nibble_to_7seg;
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begin
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begin
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mpu: entity work.mips_mpu
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mpu: entity work.mips_soc
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generic map (
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generic map (
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OBJ_CODE => obj_code,
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CLOCK_FREQ => CLOCK_FREQ,
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CLOCK_FREQ => CLOCK_FREQ,
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SRAM_ADDR_SIZE => SRAM_ADDR_SIZE
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SRAM_ADDR_SIZE => SRAM_ADDR_SIZE
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)
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)
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port map (
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port map (
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interrupt => "00000000",
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interrupt => "00000000",
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hex_display_register:
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hex_display_register:
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process(clk)
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process(clk)
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begin
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begin
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if clk'event and clk='1' then
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if clk'event and clk='1' then
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if io_byte_we/="0000" and io_wr_addr(15 downto 12)=X"2" then
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if io_byte_we/="0000" and io_wr_addr(15 downto 12)=X"2" then
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reg_display(15 downto 0) <= io_wr_data(15 downto 0);
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--reg_display(15 downto 0) <= io_wr_data(15 downto 0);
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--reg_display <= mpu_sram_address;
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reg_display <= mpu_sram_address;
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end if;
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end if;
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end if;
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end if;
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end process hex_display_register;
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end process hex_display_register;
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sd_control_register:
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sd_control_register:
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Line 456... |
-- QUAD 7-SEGMENT DISPLAYS
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-- QUAD 7-SEGMENT DISPLAYS
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--##############################################################################
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--##############################################################################
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-- Show contents of debug register in hex display
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-- Show contents of debug register in hex display
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display_data <=
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display_data <=
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reg_display(15 downto 0);-- when switches(0)='0' else
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reg_display(15 downto 0) when switches(0)='0' else
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--reg_display(31 downto 16);
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reg_display(31 downto 16);
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-- 7-segment encoders; the dev board displays are not multiplexed or encoded
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-- 7-segment encoders; the dev board displays are not multiplexed or encoded
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hex3 <= nibble_to_7seg(display_data(15 downto 12));
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hex3 <= nibble_to_7seg(display_data(15 downto 12));
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hex2 <= nibble_to_7seg(display_data(11 downto 8));
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hex2 <= nibble_to_7seg(display_data(11 downto 8));
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