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[/] [ion/] [trunk/] [vhdl/] [demo/] [c2sb_demo.vhdl] - Diff between revs 226 and 233

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--##############################################################################
--##############################################################################
-- ION MIPS-compatible CPU demo on Terasic DE-1 Cyclone-II starter board
-- ION MIPS-compatible CPU demo on Terasic DE-1 Cyclone-II starter board
--##############################################################################
--##############################################################################
-- This module is little more than a wrapper around the SoC.
-- This module is little more than a wrapper around the SoC.
-- Synthesize with 'speed' optimization for best results.
--------------------------------------------------------------------------------
 
-- Switch 9 (leftmost) is used as reset.
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- NOTE: See note at bottom of file about optional use of PLL.
-- NOTE: See note at bottom of file about optional use of PLL.
--##############################################################################
--##############################################################################
-- Copyright (C) 2011 Jose A. Ruiz
-- Copyright (C) 2011 Jose A. Ruiz
--                                                              
--                                                              
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-- Synchronization FF chain for asynchronous reset input
-- Synchronization FF chain for asynchronous reset input
signal reset_sync :         std_logic_vector(3 downto 0);
signal reset_sync :         std_logic_vector(3 downto 0);
 
 
-- Reset pushbutton debouncing logic
-- Reset pushbutton debouncing logic
subtype t_debouncer is integer range 0 to CLOCK_FREQ;
subtype t_debouncer is integer range 0 to CLOCK_FREQ*4;
constant DEBOUNCING_DELAY : t_debouncer := 500;
constant DEBOUNCING_DELAY : t_debouncer := 1500;
signal debouncing_counter : t_debouncer := (CLOCK_FREQ/1000) * DEBOUNCING_DELAY;
signal debouncing_counter : t_debouncer := (CLOCK_FREQ/1000) * DEBOUNCING_DELAY;
 
 
-- Quad 7-segment display (non multiplexed) & LEDS
-- Quad 7-segment display (non multiplexed) & LEDS
signal display_data :       std_logic_vector(15 downto 0);
signal display_data :       std_logic_vector(15 downto 0);
signal reg_gleds :          std_logic_vector(7 downto 0);
signal reg_gleds :          std_logic_vector(7 downto 0);
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begin
begin
 
 
    mpu: entity work.mips_soc
    mpu: entity work.mips_soc
    generic map (
    generic map (
        OBJ_CODE       => obj_code,
        OBJECT_CODE    => obj_code,
 
        BOOT_BRAM_SIZE => work.obj_code_pkg.BRAM_SIZE,
        CLOCK_FREQ     => CLOCK_FREQ,
        CLOCK_FREQ     => CLOCK_FREQ,
        SRAM_ADDR_SIZE => SRAM_ADDR_SIZE
        SRAM_ADDR_SIZE => SRAM_ADDR_SIZE
    )
    )
    port map (
    port map (
        interrupt   => "00000000",
        interrupt   => "00000000",
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--##############################################################################
--##############################################################################
-- RESET, CLOCK
-- RESET, CLOCK
--##############################################################################
--##############################################################################
 
 
-- Use button 3 as reset
 
-- This FF chain only prevents metastability trouble, it does not help with
-- This FF chain only prevents metastability trouble, it does not help with
-- switching bounces.
-- switching bounces.
-- (NOTE: the anti-metastability logic is probably not needed when we include 
-- (NOTE: the anti-metastability logic is probably not needed when we include 
-- the debouncing logic)
-- the debouncing logic)
reset_synchronization:
reset_synchronization:
process(clk)
process(clk)
begin
begin
    if clk'event and clk='1' then
    if clk'event and clk='1' then
        reset_sync(3) <= not buttons(2);
        reset_sync(3) <= not switches(9);
        reset_sync(2) <= reset_sync(3);
        reset_sync(2) <= reset_sync(3);
        reset_sync(1) <= reset_sync(2);
        reset_sync(1) <= reset_sync(2);
        reset_sync(0) <= reset_sync(1);
        reset_sync(0) <= reset_sync(1);
    end if;
    end if;
end process reset_synchronization;
end process reset_synchronization;

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