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[/] [ion/] [trunk/] [vhdl/] [demo/] [c2sb_demo.vhdl] - Diff between revs 46 and 59

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Rev 46 Rev 59
Line 81... Line 81...
 
 
--##############################################################################
--##############################################################################
-- 
-- 
 
 
 
 
-- CPU access to hex display (unused by Altair SW)
-- CPU access to hex display
signal reg_display :        std_logic_vector(15 downto 0);
signal reg_display :        std_logic_vector(15 downto 0);
 
 
 
 
 
 
--##############################################################################
--##############################################################################
-- DE-1 board interface signals
-- DE-1 board interface signals
 
 
 
-- Synchronization FF chain for asynchronous reset input
 
signal reset_sync :         std_logic_vector(2 downto 0);
 
 
-- Quad 7-segment display (non multiplexed) & LEDS
-- Quad 7-segment display (non multiplexed) & LEDS
signal display_data :       std_logic_vector(15 downto 0);
signal display_data :       std_logic_vector(15 downto 0);
signal reg_gleds :          std_logic_vector(7 downto 0);
signal reg_gleds :          std_logic_vector(7 downto 0);
 
 
-- i/o signals
 
signal data_io_in :         std_logic_vector(7 downto 0);
 
signal data_mem_in :        std_logic_vector(7 downto 0);
 
signal data_rom_in :        std_logic_vector(7 downto 0);
 
signal rom_access :         std_logic;
 
signal rom_space :          std_logic;
 
signal breakpoint :         std_logic;
 
 
 
 
 
-- Clock & reset signals
-- Clock & reset signals
signal clk_1hz :            std_logic;
signal clk_1hz :            std_logic;
signal clk_master :         std_logic;
signal clk_master :         std_logic;
signal counter_1hz :        std_logic_vector(25 downto 0);
signal counter_1hz :        std_logic_vector(25 downto 0);
signal reset :              std_logic;
signal reset :              std_logic;
Line 133... Line 127...
signal mpu_sram_address :   std_logic_vector(SRAM_ADDR_SIZE downto 1);
signal mpu_sram_address :   std_logic_vector(SRAM_ADDR_SIZE downto 1);
signal mpu_sram_databus :   std_logic_vector(15 downto 0);
signal mpu_sram_databus :   std_logic_vector(15 downto 0);
signal mpu_sram_byte_we_n : std_logic_vector(1 downto 0);
signal mpu_sram_byte_we_n : std_logic_vector(1 downto 0);
signal mpu_sram_oe_n :      std_logic;
signal mpu_sram_oe_n :      std_logic;
 
 
 
-- Converts hex nibble to 7-segment
 
-- Segments ordered as "GFEDCBA"; '0' is ON, '1' is OFF
 
function nibble_to_7seg(nibble : std_logic_vector(3 downto 0))
 
                        return std_logic_vector is
 
begin
 
    case nibble is
 
    when X"0"       => return "0000001";
 
    when X"1"       => return "1001111";
 
    when X"2"       => return "0010010";
 
    when X"3"       => return "0000110";
 
    when X"4"       => return "1001100";
 
    when X"5"       => return "0100100";
 
    when X"6"       => return "0100000";
 
    when X"7"       => return "0001111";
 
    when X"8"       => return "0000000";
 
    when X"9"       => return "0000100";
 
    when X"a"       => return "0001000";
 
    when X"b"       => return "1100000";
 
    when X"c"       => return "0110001";
 
    when X"d"       => return "1000010";
 
    when X"e"       => return "0110000";
 
    when X"f"       => return "0111000";
 
    when others     => return "0111111"; -- can't happen
 
    end case;
 
end function nibble_to_7seg;
 
 
 
 
begin
begin
 
 
    mpu: entity work.mips_mpu
    mpu: entity work.mips_mpu
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--##############################################################################
--##############################################################################
-- RESET, CLOCK
-- RESET, CLOCK
--##############################################################################
--##############################################################################
 
 
-- Use button 3 as reset
-- Use button 3 as reset
reset <= not buttons(3);
reset_synchronization:
 
process(clk)
 
begin
 
    if clk'event and clk='1' then
 
        reset_sync(2) <= not buttons(3);
 
        reset_sync(1) <= reset_sync(2);
 
        reset_sync(0) <= reset_sync(1);
 
    end if;
 
end process reset_synchronization;
 
 
 
reset <= reset_sync(0);
 
 
 
 
-- Generate a 1-Hz 'clock' to flash a LED for visual reference.
-- Generate a 1-Hz 'clock' to flash a LED for visual reference.
process(clk_50MHz)
process(clk_50MHz)
begin
begin
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--##############################################################################
--##############################################################################
-- QUAD 7-SEGMENT DISPLAYS
-- QUAD 7-SEGMENT DISPLAYS
--##############################################################################
--##############################################################################
 
 
-- So far, nothing to display
-- Show contents of debug register in hex display
display_data <= reg_display;
display_data <= reg_display;
 
 
 
 
-- 7-segment encoders; the dev board displays are not multiplexed or encoded
-- 7-segment encoders; the dev board displays are not multiplexed or encoded
with display_data(15 downto 12) select hex3 <=
hex3 <= nibble_to_7seg(display_data(15 downto 12));
"0000001" when X"0","1001111" when X"1","0010010" when X"2","0000110" when X"3",
hex2 <= nibble_to_7seg(display_data(11 downto  8));
"1001100" when X"4","0100100" when X"5","0100000" when X"6","0001111" when X"7",
hex1 <= nibble_to_7seg(display_data( 7 downto  4));
"0000000" when X"8","0000100" when X"9","0001000" when X"a","1100000" when X"b",
hex0 <= nibble_to_7seg(display_data( 3 downto  0));
"0110001" when X"c","1000010" when X"d","0110000" when X"e","0111000" when others;
 
 
 
with display_data(11 downto 8) select hex2 <=
 
"0000001" when X"0","1001111" when X"1","0010010" when X"2","0000110" when X"3",
 
"1001100" when X"4","0100100" when X"5","0100000" when X"6","0001111" when X"7",
 
"0000000" when X"8","0000100" when X"9","0001000" when X"a","1100000" when X"b",
 
"0110001" when X"c","1000010" when X"d","0110000" when X"e","0111000" when others;
 
 
 
with display_data(7 downto 4) select hex1 <=
 
"0000001" when X"0","1001111" when X"1","0010010" when X"2","0000110" when X"3",
 
"1001100" when X"4","0100100" when X"5","0100000" when X"6","0001111" when X"7",
 
"0000000" when X"8","0000100" when X"9","0001000" when X"a","1100000" when X"b",
 
"0110001" when X"c","1000010" when X"d","0110000" when X"e","0111000" when others;
 
 
 
with display_data(3 downto 0) select hex0 <=
 
"0000001" when X"0","1001111" when X"1","0010010" when X"2","0000110" when X"3",
 
"1001100" when X"4","0100100" when X"5","0100000" when X"6","0001111" when X"7",
 
"0000000" when X"8","0000100" when X"9","0001000" when X"a","1100000" when X"b",
 
"0110001" when X"c","1000010" when X"d","0110000" when X"e","0111000" when others;
 
 
 
--##############################################################################
--##############################################################################
-- SD card interface
-- SD card interface
--##############################################################################
--##############################################################################
 
 
-- unused in this demo, but I did not bother to cut away the attached registers
-- unused in this demo
sd_cs     <= '0';
sd_cs     <= '0';
sd_cmd    <= '0';
sd_cmd    <= '0';
sd_clk    <= '0';
sd_clk    <= '0';
sd_in     <= 'Z';
sd_in     <= 'Z';
 
 

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