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[/] [ion/] [trunk/] [vhdl/] [demo/] [c2sb_demo.vhdl] - Diff between revs 59 and 63

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Rev 59 Rev 63
Line 78... Line 78...
signal read_rx :            std_logic;
signal read_rx :            std_logic;
signal write_tx :           std_logic;
signal write_tx :           std_logic;
 
 
 
 
--##############################################################################
--##############################################################################
--
-- I/O registers
 
 
 
 
 
signal sd_clk_reg :         std_logic;
 
signal sd_cs_reg :          std_logic;
 
signal sd_cmd_reg :         std_logic;
 
signal sd_do_reg :          std_logic;
 
 
 
 
-- CPU access to hex display
-- CPU access to hex display
signal reg_display :        std_logic_vector(15 downto 0);
signal reg_display :        std_logic_vector(15 downto 0);
 
 
Line 186... Line 192...
        clk         => clk,
        clk         => clk,
        reset       => reset
        reset       => reset
    );
    );
 
 
 
 
 
--##############################################################################
 
-- I/O registers
 
--##############################################################################
 
 
 
hex_display_register:
 
process(clk)
 
begin
 
    if clk'event and clk='1' then
 
        if io_byte_we/="0000" and io_wr_addr(15 downto 12)=X"2" then
reg_display <= io_wr_data(15 downto 0);
reg_display <= io_wr_data(15 downto 0);
reg_gleds <= io_rd_vma & "000" & io_byte_we;
        end if;
 
    end if;
 
end process hex_display_register;
 
 
 
sd_control_register:
 
process(clk)
 
begin
 
    if clk'event and clk='1' then
 
        if io_byte_we/="0000" and io_wr_addr(15 downto 12)=X"1" then
 
            if io_wr_addr(5)='1' then
 
                sd_clk_reg <= io_wr_addr(4);
 
            end if;
 
            if io_wr_addr(7)='1' then
 
                sd_cs_reg <= io_wr_addr(6);
 
            end if;
 
            if io_wr_addr(11)='1' then
 
                sd_do_reg <= io_wr_data(0);
 
            end if;
 
        end if;
 
    end if;
 
end process sd_control_register;
 
 
 
 
 
-- Show the SD interface signals on the green leds for debug
 
reg_gleds <= sd_clk_reg & sd_in & sd_do_reg & "000" & sd_cmd_reg & sd_cs_reg;
 
 
 
io_rd_data(0) <= sd_in;
 
io_rd_data(31 downto 22) <= switches;
 
 
 
 
 
 
-- red leds (light with '1') -- some CPU control signals
-- red leds (light with '1') -- some CPU control signals
red_leds(0) <= '0';
red_leds(0) <= '0';
red_leds(1) <= '0';
red_leds(1) <= '0';
red_leds(2) <= '0';
red_leds(2) <= '0';
Line 296... Line 340...
 
 
--##############################################################################
--##############################################################################
-- SD card interface
-- SD card interface
--##############################################################################
--##############################################################################
 
 
-- unused in this demo
-- Connect to FFs for use in bit-banged interface
sd_cs     <= '0';
--sd_cs       <= sd_cs_reg;
sd_cmd    <= '0';
--sd_cmd      <= sd_do_reg;
sd_clk    <= '0';
--sd_clk      <= sd_clk_reg;
sd_in     <= 'Z';
--sd_data     <= 'Z' when sd_do_reg='1' else '0';
 
--sd_in       <= sd_data;
 
 
 
sd_cs       <= sd_cs_reg;
 
sd_cmd      <= sd_do_reg;
 
sd_clk      <= sd_clk_reg;
 
--sd_data     <= 'Z';-- when sd_do_reg='1' else '0';
 
sd_in       <= sd_data;
 
 
 
 
--##############################################################################
--##############################################################################
-- SERIAL
-- SERIAL
--##############################################################################
--##############################################################################

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