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[/] [ion/] [trunk/] [vhdl/] [demo/] [c2sb_demo.vhdl] - Diff between revs 63 and 75

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Rev 63 Rev 75
Line 62... Line 62... 
 
 
 
 
 
 
 
 
--##############################################################################
 
--##############################################################################
 
--
 
--
 
 
 
 
 
constant SRAM_ADDR_SIZE : integer := 18;
 
constant SRAM_ADDR_SIZE : integer := 32;
 
 
 
 
 
--##############################################################################
 
--##############################################################################
 
-- RS232 interface signals
 
-- RS232 interface signals
 
 
 
 
 
signal rx_rdy :             std_logic;
 
signal rx_rdy :             std_logic;
Line 128... Line 128... 
signal io_wr_addr :         std_logic_vector(31 downto 2);
 
signal io_wr_addr :         std_logic_vector(31 downto 2);
 
signal io_wr_data :         std_logic_vector(31 downto 0);
 
signal io_wr_data :         std_logic_vector(31 downto 0);
 
signal io_rd_vma :          std_logic;
 
signal io_rd_vma :          std_logic;
 
signal io_byte_we :         std_logic_vector(3 downto 0);
 
signal io_byte_we :         std_logic_vector(3 downto 0);
 
 
 
 
 
signal mpu_sram_address :   std_logic_vector(SRAM_ADDR_SIZE downto 1);
 
signal mpu_sram_address :   std_logic_vector(SRAM_ADDR_SIZE-1 downto 0);
 
signal mpu_sram_databus :   std_logic_vector(15 downto 0);
 
signal mpu_sram_data_rd :   std_logic_vector(15 downto 0);
 
 
 
signal mpu_sram_data_wr :   std_logic_vector(15 downto 0);
 
signal mpu_sram_byte_we_n : std_logic_vector(1 downto 0);
 
signal mpu_sram_byte_we_n : std_logic_vector(1 downto 0);
 
signal mpu_sram_oe_n :      std_logic;
 
signal mpu_sram_oe_n :      std_logic;
 
 
 
 
 
-- Converts hex nibble to 7-segment
 
-- Converts hex nibble to 7-segment
 
-- Segments ordered as "GFEDCBA"; '0' is ON, '1' is OFF
 
-- Segments ordered as "GFEDCBA"; '0' is ON, '1' is OFF
Line 179... Line 180... 
        io_rd_vma   => io_rd_vma,
 
        io_rd_vma   => io_rd_vma,
 
        io_byte_we  => io_byte_we,
 
        io_byte_we  => io_byte_we,
 
 
 
 
 
        -- interface to asynchronous 16-bit-wide EXTERNAL SRAM
 
        -- interface to asynchronous 16-bit-wide EXTERNAL SRAM
 
        sram_address    => mpu_sram_address,
 
        sram_address    => mpu_sram_address,
 
        sram_databus    => sram_data,
 
        sram_data_rd    => mpu_sram_data_rd,
 
 
 
        sram_data_wr    => mpu_sram_data_wr,
 
        sram_byte_we_n  => mpu_sram_byte_we_n,
 
        sram_byte_we_n  => mpu_sram_byte_we_n,
 
        sram_oe_n       => mpu_sram_oe_n,
 
        sram_oe_n       => mpu_sram_oe_n,
 
 
 
 
 
 
 
 
 
        uart_rxd    => rxd,
 
        uart_rxd    => rxd,
 
        uart_txd    => txd,
 
        uart_txd    => txd,
 
 
 
 
 
        clk         => clk,
 
        clk         => clk,
 
        reset       => reset
 
        reset       => reset
Line 251... Line 252... 
--##############################################################################
 
--##############################################################################
 
-- terasIC Cyclone II STARTER KIT BOARD -- interface to on-board devices
 
-- terasIC Cyclone II STARTER KIT BOARD -- interface to on-board devices
 
--##############################################################################
 
--##############################################################################
 
 
 
 
 
--##############################################################################
 
--##############################################################################
 
-- FLASH (flash is unused in this demo)
 
-- FLASH (connected to the same mup bus as the sram)
 
--##############################################################################
 
--##############################################################################
 
 
 
 
 
flash_addr <= (others => '0');
 
flash_we_n <= '1'; -- all write control signals inactive
 
flash_we_n <= '1'; -- all enable signals inactive
 
 
 
flash_oe_n <= '1';
 
 
 
flash_reset_n <= '1';
 
flash_reset_n <= '1';
 
 
 
 
 
 
 
flash_addr(21 downto 18) <= (others => '0');
 
 
 
flash_addr(17 downto  0) <= mpu_sram_address(17 downto 0); -- FIXME
 
 
 
 
 
 
 
-- Flash is decoded at 0xb0000000
 
 
 
flash_oe_n <= '0'
 
 
 
    when mpu_sram_address(31 downto 27)="10110" and mpu_sram_oe_n='0'
 
 
 
    else '1';
 
 
 
 
 
 
 
 
 
 
 
 
 
--##############################################################################
 
--##############################################################################
 
-- SRAM (used as 64K x 8)
 
-- SRAM
 
--
 
 
 
-- NOTE: All writes go to SRAM independent of rom paging status
 
 
 
--##############################################################################
 
--##############################################################################
 
 
 
 
 
sram_addr <= mpu_sram_address;
 
sram_addr <= mpu_sram_address(sram_addr'high+1 downto 1);
 
sram_oe_n <= mpu_sram_oe_n;
 
sram_oe_n <= '0'
 
 
 
    when mpu_sram_address(31 downto 27)="00000" and mpu_sram_oe_n='0'
 
 
 
    else '1';
 
 
 
 
 
sram_ub_n <= mpu_sram_byte_we_n(1) and mpu_sram_oe_n;
 
sram_ub_n <= mpu_sram_byte_we_n(1) and mpu_sram_oe_n;
 
sram_lb_n <= mpu_sram_byte_we_n(0) and mpu_sram_oe_n;
 
sram_lb_n <= mpu_sram_byte_we_n(0) and mpu_sram_oe_n;
 
sram_ce_n <= '0';
 
sram_ce_n <= '0';
 
sram_we_n <= mpu_sram_byte_we_n(1) and mpu_sram_byte_we_n(0);
 
sram_we_n <= mpu_sram_byte_we_n(1) and mpu_sram_byte_we_n(0);
 
 
 
 
 
 
 
sram_data <= mpu_sram_data_wr when mpu_sram_byte_we_n/="11" else (others => 'Z');
 
 
 
 
 
 
 
-- The only reason we need this mux is because we have the static RAM and the
 
 
 
-- static flash in separate FPGA pins, whereas in a real world application they
 
 
 
-- would be on the same data+address bus
 
 
 
mpu_sram_data_rd <=
 
 
 
    -- SRAM is decoded at 0x00000000
 
 
 
    sram_data when mpu_sram_address(31 downto 27)="00000" else
 
 
 
    X"00" & flash_data;
 
 
 
 
 
 
 
 
 
 
 
 
 
--##############################################################################
 
--##############################################################################
 
-- RESET, CLOCK
 
-- RESET, CLOCK
 
--##############################################################################
 
--##############################################################################
 
 
 
 
 
-- Use button 3 as reset
 
-- Use button 3 as reset
 
 
 
-- This FF chain only prevents metastability trouble, it does not help with
 
 
 
-- switching bounces.
 
reset_synchronization:
 
reset_synchronization:
 
process(clk)
 
process(clk)
 
begin
 
begin
 
    if clk'event and clk='1' then
 
    if clk'event and clk='1' then
 
        reset_sync(2) <= not buttons(3);
 
        reset_sync(2) <= not buttons(3);
Line 340... Line 362... 
 
 
 
 
--##############################################################################
 
--##############################################################################
 
-- SD card interface
 
-- SD card interface
 
--##############################################################################
 
--##############################################################################
 
 
 
 
 
-- Connect to FFs for use in bit-banged interface
 
-- Connect to FFs for use in bit-banged interface (still unused)
 
--sd_cs       <= sd_cs_reg;
 
 
 
--sd_cmd      <= sd_do_reg;
 
 
 
--sd_clk      <= sd_clk_reg;
 
 
 
--sd_data     <= 'Z' when sd_do_reg='1' else '0';
 
 
 
--sd_in       <= sd_data;
 
 
 
 
 
 
 
sd_cs       <= sd_cs_reg;
 
sd_cs       <= sd_cs_reg;
 
sd_cmd      <= sd_do_reg;
 
sd_cmd      <= sd_do_reg;
 
sd_clk      <= sd_clk_reg;
 
sd_clk      <= sd_clk_reg;
 
--sd_data     <= 'Z';-- when sd_do_reg='1' else '0';
 
 
 
sd_in       <= sd_data;
 
sd_in       <= sd_data;
 
 
 
 
 
 
 
 
 
--##############################################################################
 
--##############################################################################
 
-- SERIAL
 
-- SERIAL

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