Line 62... |
Line 62... |
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--##############################################################################
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--##############################################################################
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--
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--
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constant SRAM_ADDR_SIZE : integer := 18;
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constant SRAM_ADDR_SIZE : integer := 32;
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--##############################################################################
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--##############################################################################
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-- RS232 interface signals
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-- RS232 interface signals
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signal rx_rdy : std_logic;
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signal rx_rdy : std_logic;
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Line 128... |
Line 128... |
signal io_wr_addr : std_logic_vector(31 downto 2);
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signal io_wr_addr : std_logic_vector(31 downto 2);
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signal io_wr_data : std_logic_vector(31 downto 0);
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signal io_wr_data : std_logic_vector(31 downto 0);
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signal io_rd_vma : std_logic;
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signal io_rd_vma : std_logic;
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signal io_byte_we : std_logic_vector(3 downto 0);
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signal io_byte_we : std_logic_vector(3 downto 0);
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signal mpu_sram_address : std_logic_vector(SRAM_ADDR_SIZE downto 1);
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signal mpu_sram_address : std_logic_vector(SRAM_ADDR_SIZE-1 downto 0);
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signal mpu_sram_databus : std_logic_vector(15 downto 0);
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signal mpu_sram_data_rd : std_logic_vector(15 downto 0);
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signal mpu_sram_data_wr : std_logic_vector(15 downto 0);
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signal mpu_sram_byte_we_n : std_logic_vector(1 downto 0);
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signal mpu_sram_byte_we_n : std_logic_vector(1 downto 0);
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signal mpu_sram_oe_n : std_logic;
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signal mpu_sram_oe_n : std_logic;
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-- Converts hex nibble to 7-segment
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-- Converts hex nibble to 7-segment
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-- Segments ordered as "GFEDCBA"; '0' is ON, '1' is OFF
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-- Segments ordered as "GFEDCBA"; '0' is ON, '1' is OFF
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Line 179... |
Line 180... |
io_rd_vma => io_rd_vma,
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io_rd_vma => io_rd_vma,
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io_byte_we => io_byte_we,
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io_byte_we => io_byte_we,
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-- interface to asynchronous 16-bit-wide EXTERNAL SRAM
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-- interface to asynchronous 16-bit-wide EXTERNAL SRAM
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sram_address => mpu_sram_address,
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sram_address => mpu_sram_address,
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sram_databus => sram_data,
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sram_data_rd => mpu_sram_data_rd,
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sram_data_wr => mpu_sram_data_wr,
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sram_byte_we_n => mpu_sram_byte_we_n,
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sram_byte_we_n => mpu_sram_byte_we_n,
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sram_oe_n => mpu_sram_oe_n,
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sram_oe_n => mpu_sram_oe_n,
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uart_rxd => rxd,
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uart_rxd => rxd,
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uart_txd => txd,
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uart_txd => txd,
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clk => clk,
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clk => clk,
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reset => reset
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reset => reset
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Line 251... |
Line 252... |
--##############################################################################
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--##############################################################################
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-- terasIC Cyclone II STARTER KIT BOARD -- interface to on-board devices
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-- terasIC Cyclone II STARTER KIT BOARD -- interface to on-board devices
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--##############################################################################
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--##############################################################################
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--##############################################################################
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--##############################################################################
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-- FLASH (flash is unused in this demo)
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-- FLASH (connected to the same mup bus as the sram)
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--##############################################################################
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--##############################################################################
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flash_addr <= (others => '0');
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flash_we_n <= '1'; -- all write control signals inactive
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flash_we_n <= '1'; -- all enable signals inactive
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flash_oe_n <= '1';
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flash_reset_n <= '1';
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flash_reset_n <= '1';
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flash_addr(21 downto 18) <= (others => '0');
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flash_addr(17 downto 0) <= mpu_sram_address(17 downto 0); -- FIXME
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-- Flash is decoded at 0xb0000000
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flash_oe_n <= '0'
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when mpu_sram_address(31 downto 27)="10110" and mpu_sram_oe_n='0'
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else '1';
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--##############################################################################
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--##############################################################################
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-- SRAM (used as 64K x 8)
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-- SRAM
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--
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-- NOTE: All writes go to SRAM independent of rom paging status
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--##############################################################################
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--##############################################################################
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sram_addr <= mpu_sram_address;
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sram_addr <= mpu_sram_address(sram_addr'high+1 downto 1);
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sram_oe_n <= mpu_sram_oe_n;
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sram_oe_n <= '0'
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when mpu_sram_address(31 downto 27)="00000" and mpu_sram_oe_n='0'
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else '1';
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sram_ub_n <= mpu_sram_byte_we_n(1) and mpu_sram_oe_n;
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sram_ub_n <= mpu_sram_byte_we_n(1) and mpu_sram_oe_n;
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sram_lb_n <= mpu_sram_byte_we_n(0) and mpu_sram_oe_n;
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sram_lb_n <= mpu_sram_byte_we_n(0) and mpu_sram_oe_n;
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sram_ce_n <= '0';
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sram_ce_n <= '0';
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sram_we_n <= mpu_sram_byte_we_n(1) and mpu_sram_byte_we_n(0);
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sram_we_n <= mpu_sram_byte_we_n(1) and mpu_sram_byte_we_n(0);
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sram_data <= mpu_sram_data_wr when mpu_sram_byte_we_n/="11" else (others => 'Z');
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-- The only reason we need this mux is because we have the static RAM and the
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-- static flash in separate FPGA pins, whereas in a real world application they
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-- would be on the same data+address bus
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mpu_sram_data_rd <=
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-- SRAM is decoded at 0x00000000
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sram_data when mpu_sram_address(31 downto 27)="00000" else
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X"00" & flash_data;
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--##############################################################################
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--##############################################################################
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-- RESET, CLOCK
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-- RESET, CLOCK
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--##############################################################################
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--##############################################################################
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-- Use button 3 as reset
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-- Use button 3 as reset
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-- This FF chain only prevents metastability trouble, it does not help with
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-- switching bounces.
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reset_synchronization:
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reset_synchronization:
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process(clk)
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process(clk)
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begin
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begin
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if clk'event and clk='1' then
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if clk'event and clk='1' then
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reset_sync(2) <= not buttons(3);
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reset_sync(2) <= not buttons(3);
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Line 340... |
Line 362... |
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--##############################################################################
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--##############################################################################
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-- SD card interface
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-- SD card interface
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--##############################################################################
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--##############################################################################
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-- Connect to FFs for use in bit-banged interface
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-- Connect to FFs for use in bit-banged interface (still unused)
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--sd_cs <= sd_cs_reg;
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--sd_cmd <= sd_do_reg;
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--sd_clk <= sd_clk_reg;
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--sd_data <= 'Z' when sd_do_reg='1' else '0';
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--sd_in <= sd_data;
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sd_cs <= sd_cs_reg;
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sd_cs <= sd_cs_reg;
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sd_cmd <= sd_do_reg;
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sd_cmd <= sd_do_reg;
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sd_clk <= sd_clk_reg;
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sd_clk <= sd_clk_reg;
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--sd_data <= 'Z';-- when sd_do_reg='1' else '0';
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sd_in <= sd_data;
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sd_in <= sd_data;
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--##############################################################################
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--##############################################################################
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-- SERIAL
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-- SERIAL
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