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-- mips_alu.vhdl -- integer arithmetic ALU, excluding mult/div functionality.
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--
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--------------------------------------------------------------------------------
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-- Copyright (C) 2010 Jose A. Ruiz
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--
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-- This source file may be used and distributed without
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-- restriction provided that this copyright statement is not
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-- removed from the file and that any derivative work contains
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-- the original copyright notice and the associated disclaimer.
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--
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-- This source file is free software; you can redistribute it
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-- and/or modify it under the terms of the GNU Lesser General
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-- Public License as published by the Free Software Foundation;
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-- either version 2.1 of the License, or (at your option) any
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-- later version.
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--
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-- This source is distributed in the hope that it will be
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-- useful, but WITHOUT ANY WARRANTY; without even the implied
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-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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-- PURPOSE. See the GNU Lesser General Public License for more
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-- details.
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--
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-- You should have received a copy of the GNU Lesser General
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-- Public License along with this source; if not, download it
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-- from http://www.opencores.org/lgpl.shtml
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--------------------------------------------------------------------------------
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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clk : in std_logic;
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clk : in std_logic;
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reset : in std_logic;
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reset : in std_logic;
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-- function selection
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-- function selection
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ac : in t_alu_control;
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ac : in t_alu_control;
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-- comparison result flags
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flags : out t_alu_flags;
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flags : out t_alu_flags;
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-- '1' when inp1 is zero
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--flags.inp1_eq_zero : out std_logic;
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-- '1' when inp1 is < 0 (bit 31 set)
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--flags.inp1_lt_zero : out std_logic;
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-- '1' when (inp1 + ac.neg_sel(inp2) + ac.cy_in) < 0
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--flags.inp1_lt_inp2 : out std_logic;
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-- '1' when (inp1 + ac.neg_sel(inp2) + ac.cy_in) == 0
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--flags.inp1_eq_inp2 : out std_logic;
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-- data inputs
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-- data inputs
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inp1 : in std_logic_vector(31 downto 0);
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inp1 : in std_logic_vector(31 downto 0);
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inp2 : in std_logic_vector(31 downto 0);
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inp2 : in std_logic_vector(31 downto 0);
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-- data result output
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-- data result output
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outp : out std_logic_vector(31 downto 0)
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outp : out std_logic_vector(31 downto 0)
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