| Line 167... |
Line 167... |
data_wr : in std_logic_vector(31 downto 0);
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data_wr : in std_logic_vector(31 downto 0);
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mem_wait : out std_logic;
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mem_wait : out std_logic;
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cache_enable : in std_logic;
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cache_enable : in std_logic;
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ic_invalidate : in std_logic;
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ic_invalidate : in std_logic;
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-- Asserted for 1 cycle after code/data access to unmapped area
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unmapped : out std_logic;
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-- interface to FPGA i/o devices
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-- interface to FPGA i/o devices
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io_rd_data : in std_logic_vector(31 downto 0);
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io_rd_data : in std_logic_vector(31 downto 0);
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io_rd_addr : out std_logic_vector(31 downto 2);
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io_rd_addr : out std_logic_vector(31 downto 2);
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io_wr_addr : out std_logic_vector(31 downto 2);
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io_wr_addr : out std_logic_vector(31 downto 2);
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| Line 264... |
Line 266... |
data_ignore_write, -- hook for raising error flag FIXME untested
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data_ignore_write, -- hook for raising error flag FIXME untested
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data_ignore_read, -- hook for raising error flag FIXME untested
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data_ignore_read, -- hook for raising error flag FIXME untested
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-- Other states -------------------------------------------------
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-- Other states -------------------------------------------------
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--code_wait_for_dcache, -- wait for D-cache to stop using the buses
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bug -- caught an error in the state machine
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bug -- caught an error in the state machine
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);
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);
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-- Cache state machine state register & next state
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-- Cache state machine state register & next state
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signal ps, ns : t_cache_state;
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signal ps, ns : t_cache_state;
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| Line 415... |
Line 416... |
case data_wr_attr.mem_type is
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case data_wr_attr.mem_type is
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when MT_BRAM => ns <= data_ignore_write;
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when MT_BRAM => ns <= data_ignore_write;
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when MT_SRAM_16B => ns <= data_writethrough_sram_0a;
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when MT_SRAM_16B => ns <= data_writethrough_sram_0a;
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when MT_IO_SYNC => ns <= data_write_io_0;
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when MT_IO_SYNC => ns <= data_write_io_0;
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-- FIXME ignore write to undecoded area (clear pending flag)
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-- FIXME ignore write to undecoded area (clear pending flag)
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when others => ns <= ps;
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when others => ns <= data_ignore_write;
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end case;
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end case;
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elsif read_pending='1' then
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elsif read_pending='1' then
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case data_rd_attr.mem_type is
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case data_rd_attr.mem_type is
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when MT_BRAM => ns <= data_refill_bram_0;
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when MT_BRAM => ns <= data_refill_bram_0;
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| Line 453... |
Line 454... |
case data_wr_attr.mem_type is
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case data_wr_attr.mem_type is
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when MT_BRAM => ns <= data_ignore_write;
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when MT_BRAM => ns <= data_ignore_write;
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when MT_SRAM_16B => ns <= data_writethrough_sram_0a;
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when MT_SRAM_16B => ns <= data_writethrough_sram_0a;
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when MT_IO_SYNC => ns <= data_write_io_0;
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when MT_IO_SYNC => ns <= data_write_io_0;
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-- FIXME ignore write to undecoded area (clear pending flag)
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-- FIXME ignore write to undecoded area (clear pending flag)
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when others => ns <= ps;
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when others => ns <= data_ignore_write;
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end case;
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end case;
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elsif read_pending='1' then
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elsif read_pending='1' then
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case data_rd_attr.mem_type is
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case data_rd_attr.mem_type is
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when MT_BRAM => ns <= data_refill_bram_0;
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when MT_BRAM => ns <= data_refill_bram_0;
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| Line 491... |
Line 492... |
case data_wr_attr.mem_type is
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case data_wr_attr.mem_type is
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when MT_BRAM => ns <= data_ignore_write;
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when MT_BRAM => ns <= data_ignore_write;
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when MT_SRAM_16B => ns <= data_writethrough_sram_0a;
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when MT_SRAM_16B => ns <= data_writethrough_sram_0a;
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when MT_IO_SYNC => ns <= data_write_io_0;
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when MT_IO_SYNC => ns <= data_write_io_0;
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-- FIXME ignore write to undecoded area (clear pending flag)
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-- FIXME ignore write to undecoded area (clear pending flag)
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when others => ns <= ps;
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when others => ns <= data_ignore_write;
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end case;
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end case;
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elsif read_pending='1' then
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elsif read_pending='1' then
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case data_rd_attr.mem_type is
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case data_rd_attr.mem_type is
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when MT_BRAM => ns <= data_refill_bram_0;
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when MT_BRAM => ns <= data_refill_bram_0;
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| Line 664... |
Line 665... |
else
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else
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ns <= idle;
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ns <= idle;
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end if;
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end if;
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when data_ignore_write =>
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when data_ignore_write =>
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-- Access to unmapped area. We have 1 cycle to do something.
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ns <= idle;
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ns <= idle;
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when data_ignore_read =>
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when data_ignore_read =>
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-- Access to unmapped area. We have 1 cycle to do something.
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ns <= idle;
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ns <= idle;
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-- Exception states (something went wrong) ----------------------
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-- Exception states (something went wrong) ----------------------
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when code_crash =>
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when code_crash =>
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-- Attempted to fetch from i/o area. This is a software bug, probably,
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-- Attempted to fetch from i/o area. This is a software bug, probably,
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-- and should trigger a trap. We have 1 cycle to do something about it.
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-- and should trigger a trap. We have 1 cycle to do something about it.
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-- FIXME do something about wrong fetch: trap, etc.
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-- After this cycle, back to normal.
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-- After this cycle, back to normal.
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ns <= idle;
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ns <= idle;
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when bug =>
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when bug =>
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-- Something weird happened, we have 1 cycle to do something like raise
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-- Something weird happened, we have 1 cycle to do something like raise
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| Line 856... |
Line 858... |
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code_rd_attr <= decode_addr(code_rd_addr_mask);
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code_rd_attr <= decode_addr(code_rd_addr_mask);
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data_rd_attr <= decode_addr(data_rd_addr_mask);
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data_rd_attr <= decode_addr(data_rd_addr_mask);
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data_wr_attr <= decode_addr(data_wr_addr_mask);
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data_wr_attr <= decode_addr(data_wr_addr_mask);
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-- Unmapped area access flag, raised for 1 cycle only after each wrong access
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with ps select unmapped <=
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'1' when code_crash,
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'1' when data_ignore_read,
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'1' when data_ignore_write,
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'0' when others;
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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-- BRAM interface (BRAM is FPGA Block RAM)
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-- BRAM interface (BRAM is FPGA Block RAM)
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-- BRAM address can come from code or data buses, we support code execution
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-- BRAM address can come from code or data buses, we support code execution
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