| Line 92... |
Line 92... |
-- @note4: Startup values for the cache tables
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-- @note4: Startup values for the cache tables
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--
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--
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-- The cache tables has been given startup values; these are only for simulation
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-- The cache tables has been given startup values; these are only for simulation
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-- convenience and have no effect on the cache behaviour (and obviuosly they
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-- convenience and have no effect on the cache behaviour (and obviuosly they
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-- are only used after FPGA config, not after reset).
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-- are only used after FPGA config, not after reset).
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--
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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-- This module interfaces the CPU to the following:
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-- This module interfaces the CPU to the following:
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--
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--
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-- 1.- Internal 32-bit-wide BRAM for read only
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-- 1.- Internal 32-bit-wide BRAM for read only
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-- 2.- Internal 32-bit I/O bus
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-- 2.- Internal 32-bit I/O bus
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| Line 399... |
Line 400... |
signal data_miss : std_logic;
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signal data_miss : std_logic;
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-- Data miss logic, portion used with cache enabledº
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-- Data miss logic, portion used with cache enabledº
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signal data_miss_cached : std_logic;
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signal data_miss_cached : std_logic;
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-- Data miss logic, portion used with cach disabled
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-- Data miss logic, portion used with cach disabled
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signal data_miss_uncached : std_logic;
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signal data_miss_uncached : std_logic;
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-- Active when LW follows right after a SW (see caveats in code below)
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signal data_miss_by_invalidation : std_logic;
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-- Active when the data tag comparison result is valid (1 cycle after rd_vma)
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-- Active when the data tag comparison result is valid (1 cycle after rd_vma)
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-- Note: no relation to byte_we.
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-- Note: no relation to byte_we.
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signal data_tag_match_valid:std_logic;
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signal data_tag_match_valid:std_logic;
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-- Active when the D-cache state machine stalls the pipeline (mem_wait)
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-- Active when the D-cache state machine stalls the pipeline (mem_wait)
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signal data_wait : std_logic;
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signal data_wait : std_logic;
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| Line 503... |
Line 506... |
case data_wr_attr.mem_type is
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case data_wr_attr.mem_type is
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when MT_BRAM => ns <= data_ignore_write;
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when MT_BRAM => ns <= data_ignore_write;
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when MT_SRAM_16B => ns <= data_writethrough_sram_0a;
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when MT_SRAM_16B => ns <= data_writethrough_sram_0a;
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when MT_IO_SYNC => ns <= data_write_io_0;
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when MT_IO_SYNC => ns <= data_write_io_0;
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-- FIXME ignore write to undecoded area (clear pending flag)
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-- FIXME ignore write to undecoded area (clear pending flag)
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when others => ns <= ps;
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when others => ns <= data_ignore_write;
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end case;
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end case;
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elsif read_pending='1' then
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elsif read_pending='1' then
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case data_rd_attr.mem_type is
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case data_rd_attr.mem_type is
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when MT_BRAM => ns <= data_refill_bram_0;
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when MT_BRAM => ns <= data_refill_bram_0;
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| Line 541... |
Line 544... |
case data_wr_attr.mem_type is
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case data_wr_attr.mem_type is
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when MT_BRAM => ns <= data_ignore_write;
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when MT_BRAM => ns <= data_ignore_write;
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when MT_SRAM_16B => ns <= data_writethrough_sram_0a;
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when MT_SRAM_16B => ns <= data_writethrough_sram_0a;
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when MT_IO_SYNC => ns <= data_write_io_0;
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when MT_IO_SYNC => ns <= data_write_io_0;
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-- FIXME ignore write to undecoded area (clear pending flag)
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-- FIXME ignore write to undecoded area (clear pending flag)
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when others => ns <= ps;
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when others => ns <= data_ignore_write;
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end case;
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end case;
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elsif read_pending='1' then
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elsif read_pending='1' then
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case data_rd_attr.mem_type is
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case data_rd_attr.mem_type is
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when MT_BRAM => ns <= data_refill_bram_0;
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when MT_BRAM => ns <= data_refill_bram_0;
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| Line 1133... |
Line 1136... |
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-- The D-Cache misses when the tag in the cache is not the tag we want or
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-- The D-Cache misses when the tag in the cache is not the tag we want or
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-- it is not valid.
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-- it is not valid.
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-- When we write to a line right before we read from it, we have a RAW data
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-- hazard: the data cache will (usually) hit because the tag match will be done
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-- before the writethrough. To prevent this, we do an additional tag match.
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data_miss_by_invalidation <= '1' when
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data_tag_match_valid='1' and update_data_tag='1' --and
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-- FIXME skip additional tag match, it's too slow. Do later as registered
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-- match and update state machine.
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-- This means that a sequence SW + LW will ALWAYS produce a data miss,
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-- even if the written lines are different. This needs fixing.
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-- data_tag_reg=data_tag
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else '0';
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-- When cache is disabled, assert 'miss' after vma
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-- When cache is disabled, assert 'miss' after vma
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data_miss_uncached <= data_tag_match_valid and not ic_invalidate;
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data_miss_uncached <= data_tag_match_valid and not ic_invalidate;
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-- When cache is enabled, assert 'miss' after the comparison is done.
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-- When cache is enabled, assert 'miss' after the comparison is done.
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data_tags_match <= '1' when (data_tag_reg = data_cache_tag) else '0';
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data_tags_match <= '1' when (data_tag_reg = data_cache_tag) else '0';
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data_miss_cached <= '1' when data_tag_match_valid='1' and data_tags_match='0'
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data_miss_cached <= '1' when
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(data_tag_match_valid='1' and data_tags_match='0') or
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data_miss_by_invalidation='1'
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else '0';
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else '0';
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-- Select the proper code_miss signal
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-- Select the proper code_miss signal
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data_miss <= data_miss_uncached when cache_enable='0' else data_miss_cached;
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data_miss <= data_miss_uncached when cache_enable='0' else data_miss_cached;
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| Line 1269... |
Line 1286... |
-- FIXME should add a SRAM CE\ signal
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-- FIXME should add a SRAM CE\ signal
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-- SRAM address bus (except for LSB) comes from cpu code or data addr registers
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-- SRAM address bus (except for LSB) comes from cpu code or data addr registers
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sram_address(sram_address'high downto 2) <=
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sram_address(sram_address'high downto 2) <=
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data_rd_addr_reg(sram_address'high downto 2)
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data_refill_addr(sram_address'high downto 2)
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when (ps=data_refill_sram_0 or ps=data_refill_sram_1 or
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when (ps=data_refill_sram_0 or ps=data_refill_sram_1 or
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ps=data_refill_sram8_0 or ps=data_refill_sram8_1 or
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ps=data_refill_sram8_0 or ps=data_refill_sram8_1 or
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ps=data_refill_sram8_2 or ps=data_refill_sram8_3) else
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ps=data_refill_sram8_2 or ps=data_refill_sram8_3) else
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code_refill_addr(sram_address'high downto 2)
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code_refill_addr(sram_address'high downto 2)
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when (ps=code_refill_sram_0 or ps=code_refill_sram_1 or
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when (ps=code_refill_sram_0 or ps=code_refill_sram_1 or
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