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--     Currently it works because the FPGA hold tines (including an input mux

--     Currently it works because the FPGA hold tines (including an input mux

--     in the parent module) are far smaller than the SRAM response times, but

--     in the parent module) are far smaller than the SRAM response times, but

--     it would be better to insert an extra cycle after the wait states in

--     it would be better to insert an extra cycle after the wait states in

--     the sram read state machine.

--     the sram read state machine.

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