URL
https://opencores.org/ocsvn/ion/ion/trunk
[/] [ion/] [trunk/] [vhdl/] [mips_cache.vhdl] - Diff between revs 162 and 201
Go to most recent revision |
Show entire file |
Details |
Blame |
View Log
| Rev 162 |
Rev 201 |
| Line 22... |
Line 22... |
-- succesive reads from the same line will refill the entire line. This
|
-- succesive reads from the same line will refill the entire line. This
|
-- simplifies the cache logic a lot but slows uncached code a lot. Which means
|
-- simplifies the cache logic a lot but slows uncached code a lot. Which means
|
-- you should initialize the cache and enable it ASAP after reset.
|
-- you should initialize the cache and enable it ASAP after reset.
|
--
|
--
|
-- 2.- When bits CP0[12].17:16 = "01", the CPU can invalidate a cache line N
|
-- 2.- When bits CP0[12].17:16 = "01", the CPU can invalidate a cache line N
|
-- by writing word N to ANY address. The address will be executed as normal AND
|
-- by writing word N to ANY address. The write will be executed as normal AND
|
-- the cache controller will invalidate I-Cache line N.
|
-- the cache controller will invalidate I-Cache line N.
|
--
|
--
|
-- Note that the standard behavior for bits 17 and 16 of the SR is not
|
-- Note that the standard behavior for bits 17 and 16 of the SR is not
|
-- implemented at all -- no cache swapping, etc.
|
-- implemented at all -- no cache swapping, etc.
|
--
|
--
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.