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[/] [ion/] [trunk/] [vhdl/] [mips_cache.vhdl] - Diff between revs 162 and 201
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| Rev 162 |
Rev 201 |
| Line 22... |
Line 22... |
-- succesive reads from the same line will refill the entire line. This
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-- succesive reads from the same line will refill the entire line. This
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-- simplifies the cache logic a lot but slows uncached code a lot. Which means
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-- simplifies the cache logic a lot but slows uncached code a lot. Which means
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-- you should initialize the cache and enable it ASAP after reset.
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-- you should initialize the cache and enable it ASAP after reset.
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--
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--
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-- 2.- When bits CP0[12].17:16 = "01", the CPU can invalidate a cache line N
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-- 2.- When bits CP0[12].17:16 = "01", the CPU can invalidate a cache line N
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-- by writing word N to ANY address. The address will be executed as normal AND
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-- by writing word N to ANY address. The write will be executed as normal AND
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-- the cache controller will invalidate I-Cache line N.
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-- the cache controller will invalidate I-Cache line N.
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--
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--
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-- Note that the standard behavior for bits 17 and 16 of the SR is not
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-- Note that the standard behavior for bits 17 and 16 of the SR is not
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-- implemented at all -- no cache swapping, etc.
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-- implemented at all -- no cache swapping, etc.
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--
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--
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