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-- mips_cache_stub.vhdl -- cache module with no actual cache memory.
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-- mips_cache_stub.vhdl -- cache module with no actual cache memory.
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--
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--
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-- FOR SIMULATION ONLY! does not resemble structure of final cache
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--
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-- This module has the same interface as a real cache but has no cache memory.
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-- This module has the same interface as a real cache but has no cache memory.
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-- It just interfaces the CPU to the following:
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-- It just interfaces the CPU to the following:
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--
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--
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-- 1.- Internal 32-bit-wide BRAM for read and write
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-- 1.- Internal 32-bit-wide BRAM for read and write
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-- 2.- Internal 32-bit I/O bus
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-- 2.- Internal 32-bit I/O bus
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-- 3.- External 16-bit wide SRAM
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-- 3.- External 16-bit wide SRAM
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--
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--
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-- The SRAM memory interface signals are meant to connect directly to FPGA pins
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-- The purpose of this module is just to test the SRAM interface in simulation.
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-- and all outputs are registered (tco should be minimal).
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-- It will evolve to a real cache as the project goes on.
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-- SRAM data inputs are NOT registered, though. They go through a couple muxes
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-- before reaching the first register so watch out for tsetup.
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-- The SRAM is assumed to be fast enough to read or write in a clock cycle.
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--
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-- Obviously this module provides no performance gain; on the contrary, by
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-- coupling the CPU to slow external memory (16 bit bus) it actually slows it
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-- down. The purpose of this module is just to test the SRAM interface.
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--
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-- FIXME there HAS to be some explaination of the logic, it's not obvious!
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--
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--
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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