| Line 228... |
Line 228... |
-- Memory map area being accessed for each of the 3 buses:
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-- Memory map area being accessed for each of the 3 buses:
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-- 00 -> BRAM (read only)
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-- 00 -> BRAM (read only)
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-- 01 -> SRAM
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-- 01 -> SRAM
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-- 10 -> IO
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-- 10 -> IO
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-- 11 -> Unmapped
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-- 11 -> Unmapped
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signal code_rd_area : std_logic_vector(1 downto 0);
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|
signal data_rd_area : std_logic_vector(1 downto 0);
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signal code_rd_attr : t_range_attr;
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signal data_wr_area : std_logic_vector(1 downto 0);
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signal data_rd_attr : t_range_attr;
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signal data_wr_attr : t_range_attr;
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signal code_rd_type : t_memory_type;
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signal data_rd_type : t_memory_type;
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signal data_wr_type : t_memory_type;
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|
|
|
|
|
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begin
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begin
|
|
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| Line 253... |
Line 257... |
dps <= dns;
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dps <= dns;
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end if;
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end if;
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end if;
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end if;
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end process cache_state_machine_regs;
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end process cache_state_machine_regs;
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|
|
-- The code state machine occasionally 'waits' for the
|
-- (The code state machine occasionally 'waits' for the D-cache)
|
code_state_machine_transitions:
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code_state_machine_transitions:
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process(cps, dps, code_rd_vma, code_miss, code_rd_area,
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process(cps, dps, code_rd_vma, code_miss, code_rd_type,
|
write_pending, read_pending)
|
write_pending, read_pending)
|
begin
|
begin
|
case cps is
|
case cps is
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when code_normal =>
|
when code_normal =>
|
|
-- FIXME wrong logic, these signals are not active in the same cycle
|
if code_rd_vma='1' and code_miss='1' and
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if code_rd_vma='1' and code_miss='1' and
|
read_pending='0' and write_pending='0' then
|
read_pending='0' and write_pending='0' then
|
cns <= code_refill_bram_0; -- FIXME check memory area, SRAM!
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cns <= code_refill_bram_0; -- FIXME check memory area, SRAM!
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else
|
else
|
cns <= cps;
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cns <= cps;
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| Line 305... |
Line 310... |
|
|
|
|
-- This state machine does not overlap IO/BRAM/SRAM accesses for simplicity.
|
-- This state machine does not overlap IO/BRAM/SRAM accesses for simplicity.
|
|
|
data_state_machine_transitions:
|
data_state_machine_transitions:
|
process(dps, write_pending, read_pending, data_rd_area, data_wr_area)
|
process(dps, write_pending, read_pending, data_rd_type, data_wr_type)
|
begin
|
begin
|
case dps is
|
case dps is
|
when data_normal =>
|
when data_normal =>
|
if write_pending='1' then
|
if write_pending='1' then
|
case data_wr_area is
|
case data_wr_type is
|
when "00" => dns <= data_ignore_write; -- Write to BRAM ignored
|
when MT_BRAM => dns <= data_ignore_write;
|
when "01" => dns <= data_writethrough_sram_0;
|
when MT_SRAM_16B => dns <= data_writethrough_sram_0;
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when "10" => dns <= data_write_io_0;
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when MT_IO_SYNC => dns <= data_write_io_0;
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when others => dns <= dps; -- Write to undecoded area ignored
|
when others => dns <= dps; -- ignore write to undecoded area
|
end case;
|
end case;
|
|
|
elsif read_pending='1' then
|
elsif read_pending='1' then
|
case data_rd_area is
|
case data_rd_type is
|
when "00" => dns <= data_refill_bram_0;
|
when MT_BRAM => dns <= data_refill_bram_0;
|
when "01" => dns <= data_refill_sram_0;
|
when MT_SRAM_16B => dns <= data_refill_sram_0;
|
when "10" => dns <= data_read_io_0;
|
when MT_IO_SYNC => dns <= data_read_io_0;
|
when others => dns <= dps; -- ignore read from undecoded area
|
when others => dns <= dps; -- ignore read from undec. area
|
-- FIXME should raise debug flag
|
-- FIXME should raise debug flag
|
end case;
|
end case;
|
else
|
else
|
dns <= dps;
|
dns <= dps;
|
end if;
|
end if;
|
| Line 443... |
Line 448... |
code_rd_addr_mask <= code_rd_addr_reg(31 downto t_addr_decode'low);
|
code_rd_addr_mask <= code_rd_addr_reg(31 downto t_addr_decode'low);
|
data_rd_addr_mask <= data_rd_addr_reg(31 downto t_addr_decode'low);
|
data_rd_addr_mask <= data_rd_addr_reg(31 downto t_addr_decode'low);
|
data_wr_addr_mask <= data_wr_addr_reg(31 downto t_addr_decode'low);
|
data_wr_addr_mask <= data_wr_addr_reg(31 downto t_addr_decode'low);
|
|
|
|
|
with code_rd_addr_mask select code_rd_area <=
|
code_rd_attr <= decode_addr(code_rd_addr_mask);
|
"00" when ADDR_BOOT,
|
code_rd_type <= code_rd_attr(6 downto 4);
|
"01" when ADDR_XRAM,
|
|
"11" when others;
|
data_rd_attr <= decode_addr(data_rd_addr_mask);
|
|
data_rd_type <= data_rd_attr(6 downto 4);
|
with data_rd_addr_mask select data_rd_area <=
|
|
"00" when ADDR_BOOT,
|
data_wr_attr <= decode_addr(data_wr_addr_mask);
|
"01" when ADDR_XRAM,
|
data_wr_type <= data_wr_attr(6 downto 4);
|
"10" when ADDR_IO,
|
|
"11" when others;
|
|
|
--with code_rd_addr_mask select code_rd_type <=
|
with data_wr_addr_mask select data_wr_area <=
|
-- "000" when ADDR_BOOT,
|
"01" when ADDR_XRAM,
|
-- "001" when ADDR_XRAM,
|
"10" when ADDR_IO,
|
-- "011" when others;
|
"11" when others;
|
--
|
|
--with data_rd_addr_mask select data_rd_type <=
|
|
-- "000" when ADDR_BOOT,
|
|
-- "001" when ADDR_XRAM,
|
|
-- "010" when ADDR_IO,
|
|
-- "011" when others;
|
|
--
|
|
--with data_wr_addr_mask select data_wr_type <=
|
|
-- "001" when ADDR_XRAM,
|
|
-- "010" when ADDR_IO,
|
|
-- "011" when others;
|
|
|
--------------------------------------------------------------------------------
|
--------------------------------------------------------------------------------
|
-- BRAM interface
|
-- BRAM interface
|
|
|
|
|
