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[/] [ion/] [trunk/] [vhdl/] [mips_cache_stub.vhdl] - Diff between revs 72 and 73
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Rev 73 |
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-- KNOWN TROUBLE:
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-- KNOWN TROUBLE:
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--
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--
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-- Apart from the very rough looks of the code, there's a few known problems:
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-- Apart from the very rough looks of the code, there's a few known problems:
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--
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--
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-- 1.- Write address setup and hold wrt. WE\ not guaranteed
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-- 1.- Write cycles too long
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-- WE\ needs to be asserted later and deasserted earlier. The easy way
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-- In order to guarantee setup and hold times for WE controlled write
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-- would be using two extra cycles. Must find some less cosly way.
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-- cycles, two extra clock cycles are inserted for each SRAM write access.
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-- So far, in my particular test conditions, this is not giving me trouble
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-- This is the most reliable way and the easiest but probably not the best.
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-- so this will have to wait.
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-- Until I come up with something better, write cycles to SRAM are going
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-- to be very slow.
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--
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--
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-- 2.- Access to unmapped areas will crash the CPU
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-- 2.- Access to unmapped areas will crash the CPU
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-- A couple states are missing in the state machine for handling accesses
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-- A couple states are missing in the state machine for handling accesses
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-- to unmapped areas. I haven't yet decided how to handle that (return
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-- to unmapped areas. I haven't yet decided how to handle that (return
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-- zero, trigger trap, mirror another mapped area...).
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-- zero, trigger trap, mirror another mapped area...).
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