| Line 12... |
Line 12... |
--
|
--
|
-- The SRAM memory interface signals are meant to connect directly to FPGA pins
|
-- The SRAM memory interface signals are meant to connect directly to FPGA pins
|
-- and all outputs are registered (tco should be minimal).
|
-- and all outputs are registered (tco should be minimal).
|
-- SRAM data inputs are NOT registered, though. They go through a couple muxes
|
-- SRAM data inputs are NOT registered, though. They go through a couple muxes
|
-- before reaching the first register so watch out for tsetup.
|
-- before reaching the first register so watch out for tsetup.
|
-- The SRAM is assumed to be fast enough to read or write in a clock cycle.
|
|
--
|
--
|
-- Obviously this module provides no performance gain; on the contrary, by
|
-- Obviously this module provides no performance gain; on the contrary, by
|
-- coupling the CPU to slow external memory (16 bit bus) it actually slows it
|
-- coupling the CPU to slow external memory (16 bit bus) it actually slows it
|
-- down. The purpose of this module is just to test the SRAM interface and the
|
-- down. The purpose of this module is just to test the SRAM interface and the
|
-- cache logic and timing.
|
-- cache logic and timing.
|
| Line 276... |
Line 275... |
end if;
|
end if;
|
end process cache_state_machine_reg;
|
end process cache_state_machine_reg;
|
|
|
-- Unified control state machine for I-Cache and D-cache -----------------------
|
-- Unified control state machine for I-Cache and D-cache -----------------------
|
control_state_machine_transitions:
|
control_state_machine_transitions:
|
process(ps, code_rd_vma, code_miss, code_rd_attr, ws_wait_done,
|
process(ps, code_rd_vma, code_miss,
|
|
data_wr_attr.mem_type, data_rd_attr.mem_type, code_rd_attr.mem_type,
|
|
ws_wait_done,
|
write_pending, read_pending)
|
write_pending, read_pending)
|
begin
|
begin
|
case ps is
|
case ps is
|
when idle =>
|
when idle =>
|
if code_miss='1' then
|
if code_miss='1' then
|
| Line 412... |
Line 413... |
case data_wr_attr.mem_type is
|
case data_wr_attr.mem_type is
|
when MT_BRAM => ns <= data_ignore_write;
|
when MT_BRAM => ns <= data_ignore_write;
|
when MT_SRAM_16B => ns <= data_writethrough_sram_0a;
|
when MT_SRAM_16B => ns <= data_writethrough_sram_0a;
|
when MT_IO_SYNC => ns <= data_write_io_0;
|
when MT_IO_SYNC => ns <= data_write_io_0;
|
-- FIXME ignore write to undecoded area (clear pending flag)
|
-- FIXME ignore write to undecoded area (clear pending flag)
|
when others => ns <= ps;
|
when others => ns <= data_ignore_write;
|
end case;
|
end case;
|
|
|
elsif read_pending='1' then
|
elsif read_pending='1' then
|
case data_rd_attr.mem_type is
|
case data_rd_attr.mem_type is
|
when MT_BRAM => ns <= data_refill_bram_0;
|
when MT_BRAM => ns <= data_refill_bram_0;
|
