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-- mips_cache_stub.vhdl -- 1-word cache module
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-- mips_cache_stub.vhdl -- 1-word cache module
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--
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--
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-- This module has the same interface and logic as a real cache but the cache
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-- This module has the same interface and logic as a real cache but the cache
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-- memory is just 1 word for each of code and data.
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-- memory is just 1 word for each of code and data, and it's missing any tag
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-- matching logic so all accesses 'miss'.
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--
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--
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-- It interfaces the CPU to the following:
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-- It interfaces the CPU to the following:
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--
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--
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-- 1.- Internal 32-bit-wide BRAM for read only
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-- 1.- Internal 32-bit-wide BRAM for read only
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-- 2.- Internal 32-bit I/O bus
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-- 2.- Internal 32-bit I/O bus
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-- 3.- External 16-bit wide SRAM
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-- 3.- External 16-bit or 8-bit wide static memory (SRAM or FLASH)
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--
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--
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-- The SRAM memory interface signals are meant to connect directly to FPGA pins
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-- The SRAM memory interface signals are meant to connect directly to FPGA pins
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-- and all outputs are registered (tco should be minimal).
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-- and all outputs are registered (tco should be minimal).
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-- SRAM data inputs are NOT registered, though. They go through a couple muxes
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-- SRAM data inputs are NOT registered, though. They go through a couple muxes
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-- before reaching the first register so watch out for tsetup.
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-- before reaching the first register so watch out for tsetup.
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-- 2.- Access to unmapped areas will crash the CPU
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-- 2.- Access to unmapped areas will crash the CPU
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-- A couple states are missing in the state machine for handling accesses
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-- A couple states are missing in the state machine for handling accesses
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-- to unmapped areas. I haven't yet decided how to handle that (return
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-- to unmapped areas. I haven't yet decided how to handle that (return
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-- zero, trigger trap, mirror another mapped area...).
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-- zero, trigger trap, mirror another mapped area...).
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--
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--
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-- 3.- Code refills from SRAM is unimplemented yet
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-- 3.- Does not work as a real 1-word cache yet
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-- To be done for sheer lack of time.
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--
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-- 4.- Does not work as a real 1-word cache yet
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-- That functionality is still missing, all accesses 'miss'. It should be
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-- That functionality is still missing, all accesses 'miss'. It should be
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-- implemented, as a way to test the real cache logic on a small scale.
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-- implemented, as a way to test the real cache logic on a small scale.
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--
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--
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--------------------------------------------------------------------------------
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use work.mips_pkg.all;
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use work.mips_pkg.all;
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entity mips_cache_stub is
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entity mips_cache_stub is
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generic (
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generic (
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BRAM_ADDR_SIZE : integer := 10;
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BRAM_ADDR_SIZE : integer := 10; -- BRAM address size
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SRAM_ADDR_SIZE : integer := 17
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SRAM_ADDR_SIZE : integer := 17; -- Static RAM/Flash address size
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-- these cache parameters are unused in thie implementation, they're
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-- here for compatibility to the real cache module.
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LINE_SIZE : integer := 4; -- Line size in words
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CACHE_SIZE : integer := 256 -- I- and D- cache size in lines
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);
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);
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port(
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port(
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clk : in std_logic;
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clk : in std_logic;
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reset : in std_logic;
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reset : in std_logic;
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-- Interface to CPU core
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-- Interface to CPU core
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data_rd_addr : in std_logic_vector(31 downto 0);
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data_addr : in std_logic_vector(31 downto 0);
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data_rd : out std_logic_vector(31 downto 0);
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data_rd : out std_logic_vector(31 downto 0);
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data_rd_vma : in std_logic;
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data_rd_vma : in std_logic;
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byte_we : in std_logic_vector(3 downto 0);
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data_wr : in std_logic_vector(31 downto 0);
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code_rd_addr : in std_logic_vector(31 downto 2);
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code_rd_addr : in std_logic_vector(31 downto 2);
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code_rd : out std_logic_vector(31 downto 0);
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code_rd : out std_logic_vector(31 downto 0);
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code_rd_vma : in std_logic;
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code_rd_vma : in std_logic;
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data_wr_addr : in std_logic_vector(31 downto 2);
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byte_we : in std_logic_vector(3 downto 0);
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data_wr : in std_logic_vector(31 downto 0);
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mem_wait : out std_logic;
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mem_wait : out std_logic;
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cache_enable : in std_logic;
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cache_enable : in std_logic;
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-- interface to FPGA i/o devices
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-- interface to FPGA i/o devices
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io_rd_data : in std_logic_vector(31 downto 0);
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io_rd_data : in std_logic_vector(31 downto 0);
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-- Raise 'read_pending' at 1st cycle of a data read, clear it when
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-- Raise 'read_pending' at 1st cycle of a data read, clear it when
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-- the read (and/or refill) operation has been done.
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-- the read (and/or refill) operation has been done.
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-- data_rd_addr_reg always has the addr of any pending read
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-- data_rd_addr_reg always has the addr of any pending read
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if data_rd_vma='1' then
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if data_rd_vma='1' then
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read_pending <= '1';
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read_pending <= '1';
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data_rd_addr_reg <= data_rd_addr(31 downto 2);
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data_rd_addr_reg <= data_addr(31 downto 2);
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elsif ps=data_refill_sram_1 or
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elsif ps=data_refill_sram_1 or
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ps=data_refill_sram8_3 or
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ps=data_refill_sram8_3 or
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ps=data_refill_bram_1 or
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ps=data_refill_bram_1 or
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ps=data_read_io_0 or
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ps=data_read_io_0 or
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ps=data_ignore_read then
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ps=data_ignore_read then
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-- the write (writethrough actually) operation has been done.
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-- the write (writethrough actually) operation has been done.
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-- data_wr_addr_reg always has the addr of any pending write
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-- data_wr_addr_reg always has the addr of any pending write
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if byte_we/="0000" and ps=idle then
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if byte_we/="0000" and ps=idle then
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byte_we_reg <= byte_we;
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byte_we_reg <= byte_we;
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data_wr_reg <= data_wr;
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data_wr_reg <= data_wr;
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data_wr_addr_reg <= data_wr_addr;
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data_wr_addr_reg <= data_addr(31 downto 2);
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write_pending <= '1';
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write_pending <= '1';
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elsif ps=data_writethrough_sram_1b or
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elsif ps=data_writethrough_sram_1b or
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ps=data_write_io_0 or
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ps=data_write_io_0 or
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ps=data_ignore_write then
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ps=data_ignore_write then
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write_pending <= '0';
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write_pending <= '0';
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ps=code_refill_sram8_3 or
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ps=code_refill_sram8_3 or
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ps=code_refill_sram_1)
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ps=code_refill_sram_1)
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else '0';
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else '0';
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-- The lowest addr bit will only be used when accessing byte-wide memory, and
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-- The lowest addr bit will only be used when accessing byte-wide memory, and
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-- even when we're reading word-aligned code (we need to read the four bytes)
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-- even when we're reading word-aligned code (because we need to read the four
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-- bytes one by one).
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sram_address(0) <=
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sram_address(0) <=
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'0' when (ps=data_refill_sram8_0 or ps=data_refill_sram8_2 or
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'0' when (ps=data_refill_sram8_0 or ps=data_refill_sram8_2 or
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ps=code_refill_sram8_0 or ps=code_refill_sram8_2) else
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ps=code_refill_sram8_0 or ps=code_refill_sram8_2) else
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'1';
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'1';
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