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Line 2... |
-- ion_cpu.vhdl -- MIPS-I(tm) compatible CPU core
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-- ion_cpu.vhdl -- MIPS-I(tm) compatible CPU core
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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-- project: ION (http://www.opencores.org/project,ion_cpu)
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-- project: ION (http://www.opencores.org/project,ion_cpu)
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-- author: Jose A. Ruiz (ja_rd@hotmail.com)
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-- author: Jose A. Ruiz (ja_rd@hotmail.com)
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-- created: Jan/11/2011
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-- created: Jan/11/2011
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-- last modified: Mar/03/2011 (ja_rd@hotmail.com)
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-- last modified: Mar/26/2011 (ja_rd@hotmail.com)
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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-- Software placed into the public domain by the author. Use under the terms of
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-- Software placed into the public domain by the author. Use under the terms of
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-- the GPL.
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-- the GPL.
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-- Software 'as is' without warranty. Author liable for nothing.
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-- Software 'as is' without warranty. Author liable for nothing.
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--
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--
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| Line 62... |
Line 62... |
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code_rd_addr : out std_logic_vector(31 downto 2);
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code_rd_addr : out std_logic_vector(31 downto 2);
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code_rd : in std_logic_vector(31 downto 0);
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code_rd : in std_logic_vector(31 downto 0);
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code_rd_vma : out std_logic;
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code_rd_vma : out std_logic;
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cache_enable : out std_logic;
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ic_invalidate : out std_logic;
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mem_wait : in std_logic
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mem_wait : in std_logic
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);
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);
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end; --entity mips_cpu
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end; --entity mips_cpu
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architecture rtl of mips_cpu is
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architecture rtl of mips_cpu is
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Line 194... |
signal stalled_memwait : std_logic;
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signal stalled_memwait : std_logic;
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signal stalled_muldiv : std_logic;
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signal stalled_muldiv : std_logic;
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-- pipeline is stalled because of a load instruction interlock
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-- pipeline is stalled because of a load instruction interlock
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signal stalled_interlock : std_logic;
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signal stalled_interlock : std_logic;
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signal reset_done : std_logic;
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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-- CP0 registers and signals
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-- CP0 registers and signals
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-- CP0[12]: status register
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-- CP0[12]: status register
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signal cp0_status : std_logic_vector(1 downto 0);
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signal cp0_status : std_logic_vector(1 downto 0);
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-- CP0[12]: status register, cache control
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signal cp0_cache_control : std_logic_vector(17 downto 16);
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-- Output of CP0 register bank (only a few regs are implemented)
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-- Output of CP0 register bank (only a few regs are implemented)
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signal cp0_reg_read : t_word;
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signal cp0_reg_read : t_word;
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-- CP0[14]: EPC register (PC value saved at exceptions)
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-- CP0[14]: EPC register (PC value saved at exceptions)
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signal cp0_epc : t_pc;
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signal cp0_epc : t_pc;
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-- CP0[13]: 'Cause' register (cause and attributes of exception)
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-- CP0[13]: 'Cause' register (cause and attributes of exception)
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Line 456... |
if clk'event and clk='1' then
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if clk'event and clk='1' then
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if reset='1' then
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if reset='1' then
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-- reset to <vector>-4 so that 1st fetch addr is <vector>
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-- reset to <vector>-4 so that 1st fetch addr is <vector>
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p0_pc_reg <= RESET_VECTOR_M4(31 downto 2);
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p0_pc_reg <= RESET_VECTOR_M4(31 downto 2);
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else
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else
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if reset_done='1' then
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-- p0_pc_reg holds the same value as external sync ram addr register
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-- p0_pc_reg holds the same value as external sync ram addr register
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p0_pc_reg <= p0_pc_next;
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p0_pc_reg <= p0_pc_next;
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-- p0_pc_restart = addr saved to EPC on interrupts (@note2)
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-- p0_pc_restart = addr saved to EPC on interrupts (@note2)
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-- It's the addr of the instruction triggering the exception,
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-- It's the addr of the instruction triggering the exception,
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-- except when the triggering instruction is in a delay slot. In
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-- except when the triggering instruction is in a delay slot. In
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| Line 466... |
Line 473... |
else
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else
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cp0_in_delay_slot <= '1'; -- in a delay slot
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cp0_in_delay_slot <= '1'; -- in a delay slot
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end if;
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end if;
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end if;
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end if;
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end if;
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end if;
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end if;
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end process pc_register;
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end process pc_register;
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-- Common rd/wr address; lowest 2 bits are output as debugging aid only
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-- Common rd/wr address; lowest 2 bits are output as debugging aid only
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data_addr <= p1_data_addr(31 downto 0);
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data_addr <= p1_data_addr(31 downto 0);
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-- FIXME these two need to pushed behind a register, they are glitch-prone
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-- FIXME these two need to pushed behind a register, they are glitch-prone
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data_rd_vma <= p1_do_load and not pipeline_stalled; -- FIXME register
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data_rd_vma <= p1_do_load and not pipeline_stalled; -- FIXME register
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code_rd_vma <= not stall_pipeline; -- FIXME register
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code_rd_vma <= (not stall_pipeline) and reset_done; -- FIXME register
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code_rd_addr <= p0_pc_next;
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-- reset_done will be asserted after the reset process is finished, when the
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-- CPU can start operating normally.
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-- We only use it to make sure code_rd_vma is not asserted prematurely.
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wait_for_end_of_reset:
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process(clk)
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begin
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if clk'event and clk='1' then
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if reset='1' then
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reset_done <= '0';
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else
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reset_done <= '1';
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end if;
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end if;
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end process wait_for_end_of_reset;
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code_rd_addr <= p0_pc_next;
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-- compute target of J/JR instructions
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-- compute target of J/JR instructions
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p0_pc_jump <= p1_rs(31 downto 2) when p1_do_reg_jump='1' else
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p0_pc_jump <= p1_rs(31 downto 2) when p1_do_reg_jump='1' else
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p0_pc_reg(31 downto 28) & p1_ir_reg(25 downto 0);
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p0_pc_reg(31 downto 28) & p1_ir_reg(25 downto 0);
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-- compute target of relative branch instructions
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-- compute target of relative branch instructions
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| Line 962... |
Line 985... |
begin
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begin
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if clk'event and clk='1' then
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if clk'event and clk='1' then
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if reset='1' then
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if reset='1' then
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-- "10" => mode=kernel; ints=disabled
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-- "10" => mode=kernel; ints=disabled
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cp0_status <= "10";
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cp0_status <= "10";
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cp0_cache_control <= "00";
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cp0_cause_exc_code <= "00000";
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cp0_cause_exc_code <= "00000";
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cp0_cause_bd <= '0';
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cp0_cause_bd <= '0';
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else
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else
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-- no need to check for stall cycles when loading these
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-- no need to check for stall cycles when loading these
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if p1_set_cp0='1' then
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if p1_set_cp0='1' then
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-- FIXME check for CP0 reg index
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-- FIXME check for CP0 reg index
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cp0_status <= p1_rs(cp0_status'high downto 0);
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cp0_status <= p1_rs(cp0_status'high downto 0);
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cp0_cache_control <= p1_rs(17 downto 16);
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end if;
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end if;
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if p1_exception='1' and pipeline_stalled='0' then
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if p1_exception='1' and pipeline_stalled='0' then
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cp0_epc <= p0_pc_restart;
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cp0_epc <= p0_pc_restart;
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if p1_unknown_opcode='1' then
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if p1_unknown_opcode='1' then
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| Line 989... |
Line 1014... |
end if;
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end if;
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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cache_enable <= cp0_cache_control(17);
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ic_invalidate <= cp0_cache_control(16);
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cp0_cause_ce <= "00"; -- FIXME CP* traps merged with unimplemented opcode traps
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cp0_cause_ce <= "00"; -- FIXME CP* traps merged with unimplemented opcode traps
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cp0_cause <= cp0_cause_bd & '0' & cp0_cause_ce &
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cp0_cause <= cp0_cause_bd & '0' & cp0_cause_ce &
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X"00000" & "000" &
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X"00000" & "000" &
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cp0_cause_exc_code;
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cp0_cause_exc_code;
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