| Line 120... |
Line 120... |
signal p1_ac : t_alu_control;
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signal p1_ac : t_alu_control;
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-- ALU flag outputs (comparison results)
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-- ALU flag outputs (comparison results)
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signal p1_alu_flags : t_alu_flags;
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signal p1_alu_flags : t_alu_flags;
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-- immediate data, sign- or zero-extended as required by IR
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-- immediate data, sign- or zero-extended as required by IR
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signal p1_data_imm : t_word;
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signal p1_data_imm : t_word;
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signal p1_muldiv_result : t_dword;
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signal p1_branch_offset : t_pc;
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signal p1_branch_offset : t_pc;
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signal p1_branch_offset_sex:std_logic_vector(31 downto 18);
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signal p1_branch_offset_sex:std_logic_vector(31 downto 18);
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signal p1_rbank_rs_hazard : std_logic;
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signal p1_rbank_rs_hazard : std_logic;
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signal p1_rbank_rt_hazard : std_logic;
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signal p1_rbank_rt_hazard : std_logic;
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signal p1_jump_type_set0 : std_logic_vector(1 downto 0);
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signal p1_jump_type_set0 : std_logic_vector(1 downto 0);
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| Line 157... |
Line 156... |
signal p1_link : std_logic;
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signal p1_link : std_logic;
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signal p1_jump_cond_sel : std_logic_vector(2 downto 0);
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signal p1_jump_cond_sel : std_logic_vector(2 downto 0);
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signal p1_data_addr : t_addr;
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signal p1_data_addr : t_addr;
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signal p1_data_offset : t_addr;
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signal p1_data_offset : t_addr;
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signal p1_muldiv_result : t_word;
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signal p1_muldiv_func : t_mult_function;
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signal p1_muldiv_running : std_logic;
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signal p1_muldiv_started : std_logic;
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signal p1_muldiv_stall : std_logic;
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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-- Pipeline stage 2
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-- Pipeline stage 2
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signal p2_muldiv_started : std_logic;
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signal p2_exception : std_logic;
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signal p2_exception : std_logic;
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signal p2_rd_addr : std_logic_vector(1 downto 0);
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signal p2_rd_addr : std_logic_vector(1 downto 0);
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signal p2_rd_mux_control : std_logic_vector(3 downto 0);
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signal p2_rd_mux_control : std_logic_vector(3 downto 0);
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signal p2_load_target : t_regnum;
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signal p2_load_target : t_regnum;
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signal p2_do_load : std_logic;
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signal p2_do_load : std_logic;
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| Line 182... |
Line 189... |
-- pipeline is stalled for any reason
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-- pipeline is stalled for any reason
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signal pipeline_stalled : std_logic;
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signal pipeline_stalled : std_logic;
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-- pipeline is stalled because of a load instruction interlock
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-- pipeline is stalled because of a load instruction interlock
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signal pipeline_interlocked:std_logic;
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signal pipeline_interlocked:std_logic;
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--------------------------------------------------------------------------------
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-- Multiplier interface registers
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signal mdiv_hi_reg : t_word;
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signal mdiv_lo_reg : t_word;
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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-- CP0 registers and signals
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-- CP0 registers and signals
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-- CP0[12]: status register
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-- CP0[12]: status register
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-- FIXME status flags unimplemented
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-- FIXME status flags unimplemented
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| Line 325... |
Line 325... |
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p1_alu_inp1 <= p1_rs;
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p1_alu_inp1 <= p1_rs;
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with p1_alu_op2_sel select p1_alu_inp2 <=
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with p1_alu_op2_sel select p1_alu_inp2 <=
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p1_data_imm when "11",
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p1_data_imm when "11",
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p1_muldiv_result(63 downto 32) when "01",
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p1_muldiv_result when "01", -- FIXME mux input wasted!
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p1_muldiv_result(31 downto 0) when "10",
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p1_muldiv_result when "10",
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p1_rt when others;
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p1_rt when others;
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alu_inst : entity work.mips_alu
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alu_inst : entity work.mips_alu
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port map (
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port map (
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clk => clk,
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clk => clk,
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| Line 345... |
Line 345... |
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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-- Mul/Div block interface
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-- Mul/Div block interface
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-- FIXME when MUL*/DIV* are implemented, these registers and the load enable
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-- Compute the mdiv block function word. If p1_muldiv_func has any value other
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-- logic will change a little. It may be better to move them into the alu.
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-- than MULT_NOTHING a new mdiv operation will start, truncating whatever other
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mult_registers:
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-- operation that may have been in course.
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process(clk)
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-- So we encode here the function to be performed and make sure the value stays
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begin
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-- there for only one cycle (the first ALU cycle of the mul/div instruction).
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if clk'event and clk='1' then
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-- MTHI, MTLO are never involved in stall cycles, no need to check
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-- This will be '1' for all mul/div operations other than NOP...
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if p1_load_hi='1' then
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p1_muldiv_func(3) <= '1' when p1_op_special='1' and
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mdiv_hi_reg <= p1_rs;
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p1_ir_fn(5 downto 4)="01" and
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end if;
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-- ...but only if the mdiv is not already running
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if p1_load_lo='1' then
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p2_muldiv_started = '0' and
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mdiv_lo_reg <= p1_rs;
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p1_muldiv_running ='0'
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end if;
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else '0';
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end if;
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end process mult_registers;
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-- When bit(3) is zero, the rest are zeroed too. Otherwise, they come from IR
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p1_muldiv_func(2 downto 0) <=
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p1_ir_fn(3) & p1_ir_fn(1 downto 0) when p1_muldiv_func(3)='1'
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else "000";
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p1_muldiv_result <= mdiv_hi_reg & mdiv_lo_reg; -- FIXME stub, mdiv missing
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mult_div: entity work.mips_mult
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port map (
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a => p1_rs,
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b => p1_rt,
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c_mult => p1_muldiv_result,
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pause_out => p1_muldiv_running,
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mult_func => p1_muldiv_func,
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clk => clk,
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reset_in => reset
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);
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-- Active only for the 1st ALU cycle of any mul/div instruction
|
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p1_muldiv_started <= '1' when p1_op_special='1' and
|
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p1_ir_fn(5 downto 3)="011" and
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--
|
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p1_muldiv_running='0'
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else '0';
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|
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-- Stall the pipeline to enable mdiv operation completion.
|
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-- We need p2_muldiv_started to distinguish the cycle before p1_muldiv_running
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-- is asserted and the cycle after it deasserts.
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-- Otherwise we would reexecute the same muldiv endlessly instruction after
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-- deassertion of p1_muldiv_running, since the IR was stalled and still contains
|
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-- the mul opcode...
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p1_muldiv_stall <= '1' when
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-- Active for the cycle immediately before p1_muldiv_running asserts
|
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-- and NOT for the cycle after it deasserts
|
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(p1_muldiv_started='1' and p2_muldiv_started='0') or
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-- Active until operation is complete
|
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p1_muldiv_running = '1'
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else '0';
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|
|
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--##############################################################################
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--##############################################################################
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-- PC register and branch logic
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-- PC register and branch logic
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|
|
| Line 634... |
Line 667... |
p1_rbank_rt_hazard <= p0_rbank_rt_hazard;
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p1_rbank_rt_hazard <= p0_rbank_rt_hazard;
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end if;
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end if;
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end if;
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end if;
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end process pipeline_stage1_register;
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end process pipeline_stage1_register;
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|
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pipeline_stage1_register2:
|
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process(clk)
|
|
begin
|
|
if clk'event and clk='1' then
|
|
if reset='1' then
|
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p2_muldiv_started <= '0';
|
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else
|
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p2_muldiv_started <= p1_muldiv_running;
|
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end if;
|
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end if;
|
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end process pipeline_stage1_register2;
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|
|
|
|
-- Stage 2 pipeline register. Split in two for convenience.
|
-- Stage 2 pipeline register. Split in two for convenience.
|
-- This register deals with two kinds of stalls:
|
-- This register deals with two kinds of stalls:
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-- * When the pipeline stalls because of a load interlock, this register is
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-- * When the pipeline stalls because of a load interlock, this register is
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-- allowed to update so that the load operation can complete while the rest of
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-- allowed to update so that the load operation can complete while the rest of
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| Line 719... |
Line 764... |
end if;
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end if;
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end if;
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end if;
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end process pipeline_stall_registers;
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end process pipeline_stall_registers;
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|
|
-- FIXME make sure this combinational will not have bad glitches
|
-- FIXME make sure this combinational will not have bad glitches
|
stall_pipeline <= mem_wait or load_interlock;
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stall_pipeline <= mem_wait or load_interlock or p1_muldiv_stall;
|
|
|
|
|
-- FIXME load interlock should happen only if the instruction following
|
-- FIXME load interlock should happen only if the instruction following
|
-- the load actually uses the load target register. Something like this:
|
-- the load actually uses the load target register. Something like this:
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-- (p1_do_load='1' and (p1_rd_num=p0_rs_num or p1_rd_num=p0_rt_num))
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-- (p1_do_load='1' and (p1_rd_num=p0_rs_num or p1_rd_num=p0_rt_num))
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