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-- ion_cpu.vhdl -- MIPS-I(tm) compatible CPU core

-- ion_cpu.vhdl -- MIPS-I(tm) compatible CPU core

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-- project:       ION (http://www.opencores.org/project,ion_cpu)

-- project:       ION (http://www.opencores.org/project,ion_cpu)

-- author:        Jose A. Ruiz (ja_rd@hotmail.com)

-- author:        Jose A. Ruiz (ja_rd@hotmail.com)

-- created:       Jan/11/2011

-- created:       Jan/11/2011

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-- Software 'as is' without warranty.  Author liable for nothing.

-- Software 'as is' without warranty.  Author liable for nothing.

--

--

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--### MIPS-I things not implemented

--### MIPS-I things not implemented

--  # Invalid instruction trapping:

--  # Invalid instruction trapping:

--### Things with provisional implementation

--### Things with provisional implementation

-- 

-- 

-- 1.- Load interlocks: the pipeline is stalled for every load instruction, even

-- 1.- Load interlocks: the pipeline is stalled for every load instruction, even

--     if the target register is not used in the following instruction. So that

--     if the target register is not used in the following instruction. So that

--     every load takes two cycles.

--     every load takes two cycles.

--

--

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library ieee;

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_1164.all;

                    data_rd(7)  when p2_rd_addr="11" else

                    data_rd(7)  when p2_rd_addr="11" else

                    data_rd(15)  when p2_rd_addr="10" else

                    data_rd(15)  when p2_rd_addr="10" else

                    data_rd(23)  when p2_rd_addr="01" else

                    data_rd(23)  when p2_rd_addr="01" else

                    data_rd(31);

                    data_rd(31);

-- byte 0 may come from any of the 4 bytes of the input word

-- byte 0 may come from any of the 4 bytes of the input word

with p2_rd_mux_control select p2_data_word_rd(7 downto 0) <=

with p2_rd_mux_control select p2_data_word_rd(7 downto 0) <=

    data_rd(31 downto 24)        when "0000",

    data_rd(31 downto 24)        when "0000",

    data_rd(23 downto 16)        when "0001",

    data_rd(23 downto 16)        when "0001",

    data_rd(23 downto 16)        when "0100",

    data_rd(23 downto 16)        when "0100",

-- bytes 2,3 come straight from input or are extended for LH,LHU

-- bytes 2,3 come straight from input or are extended for LH,LHU

with p2_ld_upper_hword select p2_data_word_rd(31 downto 16) <=

with p2_ld_upper_hword select p2_data_word_rd(31 downto 16) <=

    (others => p2_data_word_ext) when '0',

    (others => p2_data_word_ext) when '0',

    data_rd(31 downto 16)        when others;

    data_rd(31 downto 16)        when others;

-- Select which data is to be written back to the reg bank and where

-- Select which data is to be written back to the reg bank and where

p1_rbank_wr_addr <= p1_rd_num   when p2_do_load='0' and p1_link='0' else

p1_rbank_wr_addr <= p1_rd_num   when p2_do_load='0' and p1_link='0' else

                    "11111"     when p2_do_load='0' and p1_link='1' else

                    "11111"     when p2_do_load='0' and p1_link='1' else

                    p2_load_target;

                    p2_load_target;

    p1_alu_outp                when "00",

    p1_alu_outp                when "00",

    p2_data_word_rd            when "01",

    p2_data_word_rd            when "01",

    p0_pc_incremented & "00"   when "11",

    p0_pc_incremented & "00"   when "11",

    cp0_reg_read               when others;

    cp0_reg_read               when others;

p1_rbank_we <= '1' when (p2_do_load='1' or p1_load_alu='1' or

p1_rbank_we <= '1' when (p2_do_load='1' or p1_load_alu='1' or

                        p1_link='1' or p1_get_cp0='1') and

                        p1_link='1' or p1_get_cp0='1') and

                        -- If target register is $zero, ignore write

                        -- If target register is $zero, ignore write

                        p1_rbank_wr_addr/="00000" and

                        p1_rbank_wr_addr/="00000" and

                        -- if the cache controller keeps the cpu stopped, do

                        -- if the cache controller keeps the cpu stopped, do

            p1_rs_rbank <= p1_rbank(conv_integer(p0_rs_num));

            p1_rs_rbank <= p1_rbank(conv_integer(p0_rs_num));

        end if;

        end if;

    end if;

    end if;

end process synchronous_reg_bank;

end process synchronous_reg_bank;

data_forward_register:

data_forward_register:

process(clk)

process(clk)

begin

begin

    if clk'event and clk='1' then

    if clk'event and clk='1' then

        if p1_rbank_we='1' then -- no need to check for stall cycles

        if p1_rbank_we='1' then -- no need to check for stall cycles

                      else '0';

                      else '0';

p1_rs <= p1_rs_rbank when p1_rbank_rs_hazard='0' else p1_rbank_forward;

p1_rs <= p1_rs_rbank when p1_rbank_rs_hazard='0' else p1_rbank_forward;

p1_rt <= p1_rt_rbank when p1_rbank_rt_hazard='0' else p1_rbank_forward;

p1_rt <= p1_rt_rbank when p1_rbank_rt_hazard='0' else p1_rbank_forward;

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-- ALU & ALU input multiplexors

-- ALU & ALU input multiplexors

p1_alu_inp1 <= p1_rs;

p1_alu_inp1 <= p1_rs;

end process pc_register;

end process pc_register;

-- Common rd/wr address; lowest 2 bits are output as debugging aid only

-- Common rd/wr address; lowest 2 bits are output as debugging aid only

data_addr <= p1_data_addr(31 downto 0);

data_addr <= p1_data_addr(31 downto 0);

-- reset_done will be asserted after the reset process is finished, when the

-- reset_done will be asserted after the reset process is finished, when the

-- CPU can start operating normally.

-- CPU can start operating normally.

-- We only use it to make sure code_rd_vma is not asserted prematurely.

-- We only use it to make sure code_rd_vma is not asserted prematurely.

wait_for_end_of_reset:

wait_for_end_of_reset:

            reset_done <= '1';

            reset_done <= '1';

        end if;

        end if;

    end if;

    end if;

end process wait_for_end_of_reset;

end process wait_for_end_of_reset;

code_rd_addr <= p0_pc_next;

code_rd_addr <= p0_pc_next;

-- compute target of J/JR instructions

-- compute target of J/JR instructions

p0_pc_jump <=   p1_rs(31 downto 2) when p1_do_reg_jump='1' else

p0_pc_jump <=   p1_rs(31 downto 2) when p1_do_reg_jump='1' else

                p0_pc_reg(31 downto 28) & p1_ir_reg(25 downto 0);

                p0_pc_reg(31 downto 28) & p1_ir_reg(25 downto 0);

            p1_ir_reg <= code_rd;

            p1_ir_reg <= code_rd;

        end if;

        end if;

    end if;

    end if;

end process instruction_register;

end process instruction_register;

-- 'Extract' main fields from IR, for convenience

-- 'Extract' main fields from IR, for convenience

p1_ir_op <= p1_ir_reg(31 downto 26);

p1_ir_op <= p1_ir_reg(31 downto 26);

p1_ir_fn <= p1_ir_reg(5 downto 0);

p1_ir_fn <= p1_ir_reg(5 downto 0);

-- Decode jump type, if any, for instructions with op/=0

-- Decode jump type, if any, for instructions with op/=0

with p1_ir_op select p1_jump_type_set0 <=

with p1_ir_op select p1_jump_type_set0 <=

    "10" when "000001", -- BLTZ, BGEZ, BLTZAL, BGTZAL

    "10" when "000001", -- BLTZ, BGEZ, BLTZAL, BGTZAL

    "11" when "000010", -- J

    "11" when "000010", -- J

    "11" when "000011", -- JAL

    "11" when "000011", -- JAL

    "10" when "000100", -- BEQ

    "10" when "000100", -- BEQ

    "10" when "000101", -- BNE

    "10" when "000101", -- BNE

-- Decode MTC0/MFC0 instructions

-- Decode MTC0/MFC0 instructions

p1_set_cp0 <= '1' when p1_ir_reg(31 downto 21)="01000000100" else '0';

p1_set_cp0 <= '1' when p1_ir_reg(31 downto 21)="01000000100" else '0';

p1_get_cp0 <= '1' when p1_ir_reg(31 downto 21)="01000000000" else '0';

p1_get_cp0 <= '1' when p1_ir_reg(31 downto 21)="01000000000" else '0';

p1_do_reg_jump <= '1' when p1_op_special='1' and p1_ir_fn(5 downto 1)="00100" else '0';

p1_do_reg_jump <= '1' when p1_op_special='1' and p1_ir_fn(5 downto 1)="00100" else '0';

p1_do_zero_ext_imm <= '1' when (p1_ir_op(31 downto 28)="0011") else '0';

p1_do_zero_ext_imm <= '1' when (p1_ir_op(31 downto 28)="0011") else '0';

-- Decode input data mux control (LW, LH, LB, LBU, LHU) and load enable

-- Decode input data mux control (LW, LH, LB, LBU, LHU) and load enable

p1_do_load <= '1' when

p1_do_load <= '1' when

-- Extract source and destination C0 register indices

-- Extract source and destination C0 register indices

p1_c0_rs_num <= p1_ir_reg(15 downto 11);

p1_c0_rs_num <= p1_ir_reg(15 downto 11);

p1_ac.use_slt <= '1' when (p1_ir_op="000001" and p1_ir_reg(20 downto 17)="01000") or

p1_ac.use_slt <= '1' when (p1_ir_op="000001" and p1_ir_reg(20 downto 17)="01000") or

                        (p1_ir_op="000000" and p1_ir_reg(5 downto 1)="10101") or

                        (p1_ir_op="000000" and p1_ir_reg(5 downto 1)="10101") or

                        p1_ir_op="001010" or p1_ir_op="001011"

                        p1_ir_op="001010" or p1_ir_op="001011"

               else '0';

               else '0';

                 p1_ir_reg(20 downto 16)/="10000" and -- BLTZAL is valid 

                 p1_ir_reg(20 downto 16)/="10000" and -- BLTZAL is valid 

                 p1_ir_reg(20 downto 16)/="10001")) -- BGEZAL is valid

                 p1_ir_reg(20 downto 16)/="10001")) -- BGEZAL is valid

    else '0';

    else '0';

-- Stage 1 pipeline register. Involved in ALU control.

-- Stage 1 pipeline register. Involved in ALU control.

pipeline_stage1_register:

pipeline_stage1_register:

process(clk)

process(clk)

begin

begin

        end if;

        end if;

    end if;

    end if;

end process pipeline_stage2_register_others;

end process pipeline_stage2_register_others;

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stall_pipeline <= mem_wait or load_interlock or p1_muldiv_stall;

stall_pipeline <= mem_wait or load_interlock or p1_muldiv_stall;

-- FIXME load interlock should happen only if the instruction following 

-- FIXME load interlock should happen only if the instruction following 

-- the load actually uses the load target register. Something like this:

-- the load actually uses the load target register. Something like this:

-- (p1_do_load='1' and (p1_rd_num=p0_rs_num or p1_rd_num=p0_rt_num))

-- (p1_do_load='1' and (p1_rd_num=p0_rs_num or p1_rd_num=p0_rt_num))

load_interlock <= '1' when

load_interlock <= '1' when

    p1_do_load='1' and      -- this is a load instruction

    p1_do_load='1' and      -- this is a load instruction

    pipeline_stalled='0' and -- not already stalled (i.e. assert for 1 cycle)

    pipeline_stalled='0' and -- not already stalled (i.e. assert for 1 cycle)

    (p1_rs1_hazard='1' or p1_rs2_hazard='1')

    (p1_rs1_hazard='1' or p1_rs2_hazard='1')

    else '0';

    else '0';

pipeline_stalled <= stalled_interlock or stalled_memwait or stalled_muldiv;

pipeline_stalled <= stalled_interlock or stalled_memwait or stalled_muldiv;

pipeline_stall_registers:

pipeline_stall_registers:

process(clk)

process(clk)

begin

begin

            end if;

            end if;

        end if;

        end if;

    end if;

    end if;

end process pipeline_stall_registers;

end process pipeline_stall_registers;

p1_rs1_hazard <= '1'; --'1' when p0_uses_rs1='1' and p1_rd_num=p0_rs_num else '0';

p1_rs1_hazard <= '1'; --'1' when p0_uses_rs1='1' and p1_rd_num=p0_rs_num else '0';

p1_rs2_hazard <= '1'; --'1' when p0_uses_rs2='1' and p1_rd_num=p0_rt_num else '0';

p1_rs2_hazard <= '1'; --'1' when p0_uses_rs2='1' and p1_rd_num=p0_rt_num else '0';

with p1_ir_op select p0_uses_rs1 <=

with p1_ir_op select p0_uses_rs1 <=

    '0' when "000010",

    '0' when "000010",

    '1' when "101011",

    '1' when "101011",

    '1' when "101110",

    '1' when "101110",

    '0' when others;

    '0' when others;

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p1_data_offset(31 downto 16) <= (others => p1_data_imm(15));

p1_data_offset(31 downto 16) <= (others => p1_data_imm(15));

p1_data_offset(15 downto 0) <= p1_data_imm(15 downto 0);

p1_data_offset(15 downto 0) <= p1_data_imm(15 downto 0);

p1_data_addr <= p1_rs + p1_data_offset;

p1_data_addr <= p1_rs + p1_data_offset;

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-- byte_we is a function of the write size and alignment

-- byte_we is a function of the write size and alignment

-- size = {00=1,01=2,11=4}; we 3 is MSB, 0 is LSB; big endian => 00 is msb

-- size = {00=1,01=2,11=4}; we 3 is MSB, 0 is LSB; big endian => 00 is msb

p1_we_control <= pipeline_stalled & p1_do_store & p1_store_size & p1_data_addr(1 downto 0);

p1_we_control <= pipeline_stalled & p1_do_store & p1_store_size & p1_data_addr(1 downto 0);

-- pX_* don't load.

-- pX_* don't load.

--

--

-- The register bank WE is enabled when the pipeline is not stalled and when 

-- The register bank WE is enabled when the pipeline is not stalled and when 

-- it is stalled because of a load interlock; so that in case of interlock the

-- it is stalled because of a load interlock; so that in case of interlock the

-- load operation can complete while the rest of the pipeline is frozen.

-- load operation can complete while the rest of the pipeline is frozen.

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