| Line 953... |
Line 953... |
-- Write enable vector
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-- Write enable vector
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-- byte_we is a function of the write size and alignment
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-- byte_we is a function of the write size and alignment
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-- size = {00=1,01=2,11=4}; we 3 is MSB, 0 is LSB; big endian => 00 is msb
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-- size = {00=1,01=2,11=4}; we 3 is MSB, 0 is LSB; big endian => 00 is msb
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p1_we_control <= (p2_do_store xor pipeline_stalled) & p1_do_store & p1_store_size & p1_data_addr(1 downto 0);
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p1_we_control <= (mem_wait) & p1_do_store & p1_store_size & p1_data_addr(1 downto 0);
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--p1_we_control <= (pipeline_stalled) & p1_do_store & p1_store_size & p1_data_addr(1 downto 0);
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--p1_we_control <= (pipeline_stalled) & p1_do_store & p1_store_size & p1_data_addr(1 downto 0);
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-- Bug: For two SW instructions in a row, the 2nd one will be stalled and lost:
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-- Bug: For two SW instructions in a row, the 2nd one will be stalled and lost:
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-- the write will never be executed by the cache.
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-- the write will never be executed by the cache.
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-- Fix: replaced 'pipeline_stalled' from the equation above by '0' literal.
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-- Fixed by stalling immediately after asserting byte_we.
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-- FIXME the above fix has been tested with the code samples BUT it may still
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-- FIXME the above fix has been tested but is still under trial (provisional)
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-- have unintended consequences (I forgot why 'pipeline_stalled' was there in
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-- the first place...)
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-- The present code will not work in cache-less systems (such as the tb0) if
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-- The present code will not work in cache-less systems (such as the tb0) if
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-- it stalls the CPU. Solution: don't allow stalls in cache-less systems.
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-- it stalls the CPU. Solution: don't allow stalls in cache-less systems.
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-- FIXME this little mess has to be documented.
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-- FIXME this little mess has to be documented.
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| Line 1012... |
Line 1011... |
cp0_cause_exc_code <= "00000";
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cp0_cause_exc_code <= "00000";
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cp0_cause_bd <= '0';
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cp0_cause_bd <= '0';
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else
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else
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-- no need to check for stall cycles when loading these
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-- no need to check for stall cycles when loading these
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if p1_set_cp0='1' then
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if p1_set_cp0='1' then
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-- NOTE: in MTCx, the source register is Rt
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-- FIXME check for CP0 reg index
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-- FIXME check for CP0 reg index
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cp0_status <= p1_rs(cp0_status'high downto 0);
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cp0_status <= p1_rt(cp0_status'high downto 0);
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cp0_cache_control <= p1_rs(17 downto 16);
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cp0_cache_control <= p1_rt(17 downto 16);
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end if;
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end if;
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if p1_exception='1' and pipeline_stalled='0' then
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if p1_exception='1' and pipeline_stalled='0' then
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cp0_epc <= p0_pc_restart;
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cp0_epc <= p0_pc_restart;
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if p1_unknown_opcode='1' then
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if p1_unknown_opcode='1' then
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