| Line 211... |
Line 211... |
--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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-- CP0 registers and signals
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-- CP0 registers and signals
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-- CP0[12]: status register, KUo/IEo & KUP/IEp & KU/IE bits
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-- CP0[12]: status register, KUo/IEo & KUP/IEp & KU/IE bits
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signal cp0_status : std_logic_vector(5 downto 0);
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signal cp0_status : std_logic_vector(5 downto 0);
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signal cp0_sr_ku_reg : std_logic;
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-- CP0[12]: status register, cache control
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-- CP0[12]: status register, cache control
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signal cp0_cache_control : std_logic_vector(17 downto 16);
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signal cp0_cache_control : std_logic_vector(17 downto 16);
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-- Output of CP0 register bank (only a few regs are implemented)
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-- Output of CP0 register bank (only a few regs are implemented)
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signal cp0_reg_read : t_word;
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signal cp0_reg_read : t_word;
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-- CP0[14]: EPC register (PC value saved at exceptions)
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-- CP0[14]: EPC register (PC value saved at exceptions)
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| Line 791... |
Line 792... |
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p1_cp_unavailable <= '1' when
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p1_cp_unavailable <= '1' when
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(p1_set_cp='1' and p1_set_cp0='0') or -- mtc1..3
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(p1_set_cp='1' and p1_set_cp0='0') or -- mtc1..3
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(p1_get_cp='1' and p1_get_cp0='0') or -- mfc1..3
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(p1_get_cp='1' and p1_get_cp0='0') or -- mfc1..3
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((p1_get_cp0='1' or p1_set_cp0='1' or p1_rfe='1')
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((p1_get_cp0='1' or p1_set_cp0='1' or p1_rfe='1')
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and cp0_status(1)='0') -- COP0 user mode
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and cp0_sr_ku_reg='0')
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--and cp0_status(1)='0') -- COP0 user mode
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-- FIXME CP1..3 logic missing
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else '0';
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else '0';
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--##############################################################################
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--##############################################################################
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-- Pipeline registers & pipeline control logic
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-- Pipeline registers & pipeline control logic
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| Line 1034... |
Line 1037... |
begin
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begin
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if clk'event and clk='1' then
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if clk'event and clk='1' then
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if reset='1' then
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if reset='1' then
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-- KU/IE="10" ==> mode=kernel; ints=disabled
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-- KU/IE="10" ==> mode=kernel; ints=disabled
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cp0_status <= "000010"; -- bits (KUo/IEo & KUp/IEp) reset to zero
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cp0_status <= "000010"; -- bits (KUo/IEo & KUp/IEp) reset to zero
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cp0_sr_ku_reg <= '1'; -- delayed KU flag
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cp0_cache_control <= "00";
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cp0_cache_control <= "00";
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cp0_cause_exc_code <= "00000";
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cp0_cause_exc_code <= "00000";
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cp0_cause_bd <= '0';
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cp0_cause_bd <= '0';
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else
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else
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if pipeline_stalled='0' then
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if pipeline_stalled='0' then
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| Line 1066... |
Line 1070... |
end if;
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end if;
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end if;
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end if;
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-- ... and the BD flag for exceptions in delay slots
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-- ... and the BD flag for exceptions in delay slots
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cp0_cause_bd <= cp0_in_delay_slot;
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cp0_cause_bd <= cp0_in_delay_slot;
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-- FIXME RFE missing
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elsif p1_rfe='1' and cp0_status(1)='1' then
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elsif p1_rfe='1' and cp0_status(1)='1' then
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-- RFE: restore ('pop') the KU/IE flag values
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-- RFE: restore ('pop') the KU/IE flag values
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cp0_status(3 downto 2) <= cp0_status(5 downto 4);
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cp0_status(3 downto 2) <= cp0_status(5 downto 4);
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cp0_status(1 downto 0) <= cp0_status(3 downto 2);
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cp0_status(1 downto 0) <= cp0_status(3 downto 2);
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| Line 1083... |
Line 1086... |
-- CP0[13].IP1-0 are implemented, check for CP0 reg index.
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-- CP0[13].IP1-0 are implemented, check for CP0 reg index.
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cp0_status <= p1_rt(cp0_status'high downto 0);
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cp0_status <= p1_rt(cp0_status'high downto 0);
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cp0_cache_control <= p1_rt(17 downto 16);
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cp0_cache_control <= p1_rt(17 downto 16);
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end if;
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end if;
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end if;
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end if;
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if stall_pipeline='0' then
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cp0_sr_ku_reg <= cp0_status(1);
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end if;
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end if;
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end if;
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end if;
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end if;
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end process cp0_registers;
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end process cp0_registers;
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cache_enable <= cp0_cache_control(17);
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cache_enable <= cp0_cache_control(17);
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