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[/] [ion/] [trunk/] [vhdl/] [mips_cpu.vhdl] - Diff between revs 162 and 171
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| Rev 162 |
Rev 171 |
| Line 327... |
Line 327... |
cp0_reg_read when others;
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cp0_reg_read when others;
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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-- Register bank RAM & Rbank WE logic
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-- Register bank RAM & Rbank WE logic
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p1_rbank_we <= '1' when (p2_do_load='1' or p1_load_alu='1' or
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p1_rbank_we <= '1' when (p2_do_load='1' or p1_load_alu='1' or p1_link='1' or
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p1_link='1' or p1_get_cp0='1') and
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-- if mfc0 triggers privilege trap, don't load reg
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(p1_get_cp0='1' and p1_cp_unavailable='0')) and
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-- If target register is $zero, ignore write
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-- If target register is $zero, ignore write
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p1_rbank_wr_addr/="00000" and
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p1_rbank_wr_addr/="00000" and
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-- if the cache controller keeps the cpu stopped, do
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-- if the cache controller keeps the cpu stopped, do
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-- not writeback
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-- not writeback
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mem_wait='0' and
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mem_wait='0' and
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