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-- ion_cpu.vhdl -- MIPS-I(tm) compatible CPU core
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-- ion_cpu.vhdl -- MIPS-I(tm) compatible CPU core
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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-- project: ION (http://www.opencores.org/project,ion_cpu)
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-- project: ION (http://www.opencores.org/project,ion_cpu)
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-- author: Jose A. Ruiz (ja_rd@hotmail.com)
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-- author: Jose A. Ruiz (ja_rd@hotmail.com)
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-- created: Jan/11/2011
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-- created: Jan/11/2011
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-- last modified: Jun/05/2011 (ja_rd@hotmail.com)
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-- last modified: Jul/31/2011 (ja_rd@hotmail.com)
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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-- Please read file /doc/ion_project.txt for usage instructions.
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-- Please read file /doc/ion_project.txt for usage instructions.
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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--### MIPS-I things not implemented
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--### MIPS-I things not implemented
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--
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--
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--
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--
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-- 1.- Load interlocks: the pipeline is stalled for every load instruction, even
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-- 1.- Load interlocks: the pipeline is stalled for every load instruction, even
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-- if the target register is not used in the following instruction. So that
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-- if the target register is not used in the following instruction. So that
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-- every load takes two cycles.
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-- every load takes two cycles.
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-- The interlock logic should check register indices (@note2)
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-- The interlock logic should check register indices (@note2)
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-- 2.- CP0 SR (status register) bits KUo/IEo & KUP/IEp are missing.
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-- 2.- Invalid instruction side effects:
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-- This means that EXCEPTIONS CAN'T BE NESTED in this version of the CPU.
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-- 3.- Invalid instruction side effects:
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-- Invalid opcodes do trap but the logic that prevents bad opcodes from
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-- Invalid opcodes do trap but the logic that prevents bad opcodes from
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-- having side affects has not been tested yet.
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-- having side affects has not been tested yet.
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-- 4.- Kernel/user status.
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-- 3.- Kernel/user status.
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-- When in user mode, COP* instructions will trigger a 'CpU' exception.
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-- When in user mode, COP* instructions will trigger a 'CpU' exception.
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-- BUT there's no address checking and user code can still access kernel
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-- BUT there's no address checking and user code can still access kernel
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-- space in this version.
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-- space in this version.
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-- Besides, see point 2 above about the missing SR bits.
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--
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--
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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-- KNOWN BUGS:
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-- KNOWN BUGS:
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--
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--
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-- 1.- The instruction executed right after entering user mode (i.e. the
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-- 1.- The instruction executed right after entering user mode (i.e. the
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-- instruction after the MTC0 or RFE that clears the KU flag) is executed
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-- instruction after the MTC0 or RFE that clears the KU flag) is executed
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-- in kernel mode (instead of user mode). This is a gapping security hole,
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-- in kernel mode (instead of user mode). This is a gaping security hole,
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-- in case it makes any sense to speak of security in this project at this
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-- in case it makes any sense to speak of security in this project at this
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-- stage.
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-- stage.
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-- This can be easily fixed but is not very urgent.
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-- This can be easily fixed but is not very urgent.
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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-- Copyright (C) 2011 Jose A. Ruiz
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-- Copyright (C) 2011 Jose A. Ruiz
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XILINX_REGBANK : string := "distributed" -- {distributed|block}
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XILINX_REGBANK : string := "distributed" -- {distributed|block}
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);
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);
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port(
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port(
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clk : in std_logic;
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clk : in std_logic;
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reset : in std_logic;
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reset : in std_logic;
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interrupt : in std_logic;
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interrupt : in std_logic_vector(7 downto 0);
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data_addr : out std_logic_vector(31 downto 0);
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data_addr : out std_logic_vector(31 downto 0);
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data_rd : in std_logic_vector(31 downto 0);
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data_rd : in std_logic_vector(31 downto 0);
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data_rd_vma : out std_logic;
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data_rd_vma : out std_logic;
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