OpenCores
URL https://opencores.org/ocsvn/ion/ion/trunk

Subversion Repositories ion

[/] [ion/] [trunk/] [vhdl/] [mips_cpu.vhdl] - Diff between revs 171 and 200

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 171 Rev 200
Line 2... Line 2...
-- ion_cpu.vhdl -- MIPS-I(tm) compatible CPU core
-- ion_cpu.vhdl -- MIPS-I(tm) compatible CPU core
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- project:       ION (http://www.opencores.org/project,ion_cpu)
-- project:       ION (http://www.opencores.org/project,ion_cpu)
-- author:        Jose A. Ruiz (ja_rd@hotmail.com)
-- author:        Jose A. Ruiz (ja_rd@hotmail.com)
-- created:       Jan/11/2011
-- created:       Jan/11/2011
-- last modified: Jun/05/2011 (ja_rd@hotmail.com)
-- last modified: Jul/31/2011 (ja_rd@hotmail.com)
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Please read file /doc/ion_project.txt for usage instructions.
-- Please read file /doc/ion_project.txt for usage instructions.
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
--### MIPS-I things not implemented
--### MIPS-I things not implemented
--
--
Line 17... Line 17...
-- 
-- 
-- 1.- Load interlocks: the pipeline is stalled for every load instruction, even
-- 1.- Load interlocks: the pipeline is stalled for every load instruction, even
--     if the target register is not used in the following instruction. So that
--     if the target register is not used in the following instruction. So that
--     every load takes two cycles.
--     every load takes two cycles.
--     The interlock logic should check register indices (@note2)
--     The interlock logic should check register indices (@note2)
-- 2.- CP0 SR (status register) bits KUo/IEo & KUP/IEp are missing.
-- 2.- Invalid instruction side effects:
--     This means that EXCEPTIONS CAN'T BE NESTED in this version of the CPU.
 
-- 3.- Invalid instruction side effects:
 
--     Invalid opcodes do trap but the logic that prevents bad opcodes from
--     Invalid opcodes do trap but the logic that prevents bad opcodes from
--     having side affects has not been tested yet.
--     having side affects has not been tested yet.
-- 4.- Kernel/user status.
-- 3.- Kernel/user status.
--     When in user mode, COP* instructions will trigger a 'CpU' exception.
--     When in user mode, COP* instructions will trigger a 'CpU' exception.
--     BUT there's no address checking and user code can still access kernel 
--     BUT there's no address checking and user code can still access kernel 
--     space in this version.
--     space in this version.
--     Besides, see point 2 above about the missing SR bits.
 
--
--
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- KNOWN BUGS:
-- KNOWN BUGS:
--
--
-- 1.- The instruction executed right after entering user mode (i.e. the 
-- 1.- The instruction executed right after entering user mode (i.e. the 
--     instruction after the MTC0 or RFE that clears the KU flag) is executed 
--     instruction after the MTC0 or RFE that clears the KU flag) is executed 
--     in kernel mode (instead of user mode). This is a gapping security hole,
--     in kernel mode (instead of user mode). This is a gaping security hole,
--     in case it makes any sense to speak of security in this project at this
--     in case it makes any sense to speak of security in this project at this
--     stage. 
--     stage. 
--     This can be easily fixed but is not very urgent.
--     This can be easily fixed but is not very urgent.
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Copyright (C) 2011 Jose A. Ruiz
-- Copyright (C) 2011 Jose A. Ruiz
Line 80... Line 77...
        XILINX_REGBANK  : string    := "distributed" -- {distributed|block}
        XILINX_REGBANK  : string    := "distributed" -- {distributed|block}
    );
    );
    port(
    port(
        clk             : in std_logic;
        clk             : in std_logic;
        reset           : in std_logic;
        reset           : in std_logic;
        interrupt       : in std_logic;
        interrupt       : in std_logic_vector(7 downto 0);
 
 
        data_addr       : out std_logic_vector(31 downto 0);
        data_addr       : out std_logic_vector(31 downto 0);
 
 
        data_rd         : in std_logic_vector(31 downto 0);
        data_rd         : in std_logic_vector(31 downto 0);
        data_rd_vma     : out std_logic;
        data_rd_vma     : out std_logic;

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.