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[/] [ion/] [trunk/] [vhdl/] [mips_cpu.vhdl] - Diff between revs 200 and 242
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| Rev 200 |
Rev 242 |
| Line 94... |
Line 94... |
code_rd_vma : out std_logic;
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code_rd_vma : out std_logic;
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cache_enable : out std_logic;
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cache_enable : out std_logic;
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ic_invalidate : out std_logic;
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ic_invalidate : out std_logic;
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mem_wait : in std_logic
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mem_wait : in std_logic;
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cache_ready : in std_logic
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);
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);
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end; --entity mips_cpu
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end; --entity mips_cpu
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architecture rtl of mips_cpu is
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architecture rtl of mips_cpu is
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Line 562... |
begin
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begin
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if clk'event and clk='1' then
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if clk'event and clk='1' then
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if reset='1' then
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if reset='1' then
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p1_ir_reg <= (others => '0');
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p1_ir_reg <= (others => '0');
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elsif stall_pipeline='0' then
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elsif stall_pipeline='0' then
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-- Load the IR with whatever the cache is giving us, UNLESS the
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-- cache is not ready (has not yet completed the first code refill
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-- after reset), in which case...
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if cache_ready='1' then
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p1_ir_reg <= code_rd;
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p1_ir_reg <= code_rd;
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else
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-- ... load the IR with something innocuous so that the
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-- instruction decoder does not derail.
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p1_ir_reg <= (others => '0');
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end if;
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end if;
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end if;
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end if;
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end if;
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end process instruction_register;
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end process instruction_register;
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-- Zero extension/Sign extension of instruction immediate data
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-- Zero extension/Sign extension of instruction immediate data
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