| Line 67... |
Line 67... |
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data_wr_addr : out std_logic_vector(31 downto 2);
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data_wr_addr : out std_logic_vector(31 downto 2);
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byte_we : out std_logic_vector(3 downto 0);
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byte_we : out std_logic_vector(3 downto 0);
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data_wr : out std_logic_vector(31 downto 0);
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data_wr : out std_logic_vector(31 downto 0);
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|
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-- NOTE: needs to be synchronous to clk
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mem_wait : in std_logic
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mem_wait : in std_logic
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);
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);
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end; --entity mips_cpu
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end; --entity mips_cpu
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|
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architecture rtl of mips_cpu is
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architecture rtl of mips_cpu is
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| Line 162... |
Line 161... |
signal p1_muldiv_func : t_mult_function;
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signal p1_muldiv_func : t_mult_function;
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signal p1_muldiv_running : std_logic;
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signal p1_muldiv_running : std_logic;
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signal p1_muldiv_started : std_logic;
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signal p1_muldiv_started : std_logic;
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signal p1_muldiv_stall : std_logic;
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signal p1_muldiv_stall : std_logic;
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|
|
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signal p1_unknown_opcode : std_logic;
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|
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--------------------------------------------------------------------------------
|
--------------------------------------------------------------------------------
|
-- Pipeline stage 2
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-- Pipeline stage 2
|
|
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signal p2_muldiv_started : std_logic;
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signal p2_muldiv_started : std_logic;
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| Line 325... |
Line 325... |
|
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p1_alu_inp1 <= p1_rs;
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p1_alu_inp1 <= p1_rs;
|
|
|
with p1_alu_op2_sel select p1_alu_inp2 <=
|
with p1_alu_op2_sel select p1_alu_inp2 <=
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p1_data_imm when "11",
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p1_data_imm when "11",
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p1_muldiv_result when "01", -- FIXME mux input wasted!
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p1_muldiv_result when "01",
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p1_muldiv_result when "10",
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--p1_muldiv_result when "10", -- FIXME mux input wasted!
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p1_rt when others;
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p1_rt when others;
|
|
|
alu_inst : entity work.mips_alu
|
alu_inst : entity work.mips_alu
|
port map (
|
port map (
|
clk => clk,
|
clk => clk,
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| Line 531... |
Line 531... |
not (p1_alu_flags.inp1_lt_inp2 or
|
not (p1_alu_flags.inp1_lt_inp2 or
|
p1_alu_flags.inp1_eq_inp2) when "111",
|
p1_alu_flags.inp1_eq_inp2) when "111",
|
'1' when others;
|
'1' when others;
|
|
|
-- Decode instructions that launch exceptions
|
-- Decode instructions that launch exceptions
|
p1_exception <= '1' when p1_op_special='1' and p1_ir_reg(5 downto 1)="00110"
|
p1_exception <= '1' when
|
|
(p1_op_special='1' and p1_ir_reg(5 downto 1)="00110") or
|
|
p1_unknown_opcode='1'
|
else '0';
|
else '0';
|
|
|
-- Decode MTC0/MFC0 instructions
|
-- Decode MTC0/MFC0 instructions
|
p1_set_cp0 <= '1' when p1_ir_reg(31 downto 21)="01000000100" else '0';
|
p1_set_cp0 <= '1' when p1_ir_reg(31 downto 21)="01000000100" else '0';
|
p1_get_cp0 <= '1' when p1_ir_reg(31 downto 21)="01000000000" else '0';
|
p1_get_cp0 <= '1' when p1_ir_reg(31 downto 21)="01000000000" else '0';
|
| Line 649... |
Line 651... |
"10" when (p1_ir_op="001110") else
|
"10" when (p1_ir_op="001110") else
|
"11";
|
"11";
|
|
|
p1_ac.shift_amount <= p1_ir_reg(10 downto 6) when p1_ir_fn(2)='0' else p1_rs(4 downto 0);
|
p1_ac.shift_amount <= p1_ir_reg(10 downto 6) when p1_ir_fn(2)='0' else p1_rs(4 downto 0);
|
|
|
|
|
|
--------------------------------------------------------------------------------
|
|
-- Decoding of unimplemented and privileged instructions
|
|
|
|
-- Unimplemented instructions include:
|
|
-- 1.- All instructions above architecture MIPS-I except:
|
|
-- 1.1.- eret
|
|
-- 2.- Unaligned stores and loads (LWL,LWR,SWL,SWR)
|
|
-- 3.- All CP0 instructions other than mfc0 and mtc0
|
|
-- 4.- All CPi instructions
|
|
-- 5.- All cache instructions
|
|
-- For the time being, we'll decode them all together.
|
|
|
|
-- FIXME: some of these should trap but others should just NOP (e.g. EHB)
|
|
|
|
p1_unknown_opcode <= '1' when
|
|
-- decode by 'opcode' field
|
|
p1_ir_op(31 downto 29)="011" or
|
|
p1_ir_op(31 downto 29)="110" or
|
|
p1_ir_op(31 downto 29)="111" or
|
|
(p1_ir_op(31 downto 29)="010" and p1_ir_op(28 downto 26)/="000") or
|
|
p1_ir_op="101111" or -- CACHE
|
|
p1_ir_op="100010" or -- LWL
|
|
p1_ir_op="100110" or -- LWR
|
|
p1_ir_op="101010" or -- SWL
|
|
p1_ir_op="101110" or -- SWR
|
|
p1_ir_op="100111" or
|
|
p1_ir_op="101100" or
|
|
p1_ir_op="101101" or
|
|
-- decode instructions in the 'special' opcode group
|
|
(p1_ir_op="000000" and
|
|
(p1_ir_fn(5 downto 4)="11" or
|
|
p1_ir_fn="000001" or
|
|
p1_ir_fn="000101" or
|
|
p1_ir_fn="001010" or
|
|
p1_ir_fn="001011" or
|
|
p1_ir_fn="001110" or
|
|
p1_ir_fn(5 downto 2)="0101" or
|
|
p1_ir_fn(5 downto 2)="0111" or
|
|
p1_ir_fn(5 downto 2)="1011")) or
|
|
-- decode instructions in the 'regimm' opcode group
|
|
(p1_ir_op="000001" and
|
|
(p1_ir_reg(20 downto 16)/="00000" and -- BLTZ is valid
|
|
p1_ir_reg(20 downto 16)/="00001" and -- BGEZ is valid
|
|
p1_ir_reg(20 downto 16)/="10000" and -- BLTZAL is valid
|
|
p1_ir_reg(20 downto 16)/="10001")) -- BGEZAL is valid
|
|
|
|
else '0';
|
|
|
--------------------------------------------------------------------------------
|
--------------------------------------------------------------------------------
|
|
|
-- Stage 1 pipeline register. Involved in ALU control.
|
-- Stage 1 pipeline register. Involved in ALU control.
|
pipeline_stage1_register:
|
pipeline_stage1_register:
|
process(clk)
|
process(clk)
|
