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-- ion_cpu.vhdl -- MIPS-I(tm) compatible CPU core
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-- ion_cpu.vhdl -- MIPS-I(tm) compatible CPU core
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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-- project: ION (http://www.opencores.org/project,ion_cpu)
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-- project: ION (http://www.opencores.org/project,ion_cpu)
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-- author: Jose A. Ruiz (ja_rd@hotmail.com)
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-- author: Jose A. Ruiz (ja_rd@hotmail.com)
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-- created: Jan/11/2011
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-- created: Jan/11/2011
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-- last modified: Jan/25/2011 (ja_rd@hotmail.com)
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-- last modified: Jan/31/2011 (ja_rd@hotmail.com)
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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-- Software placed into the public domain by the author. Use under the terms of
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-- Software placed into the public domain by the author. Use under the terms of
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-- the GPL.
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-- the GPL.
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-- Software 'as is' without warranty. Author liable for nothing.
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-- Software 'as is' without warranty. Author liable for nothing.
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--
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--
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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--### MIPS-I things not implemented
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--### MIPS-I things not implemented
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-- # Invalid instruction trapping:
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-- # Invalid instruction trapping:
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-- * invalid opcodes do trap but side affects not prevented yet
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-- * invalid opcodes do trap but the logic that prevents bad opcodes from
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-- having side affects has not been tested yet.
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-- # Kernel/user status
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-- # Kernel/user status
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-- # RTE instruction
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-- # RTE instruction (or ERET)
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-- # Most of the CP0 registers and of course all of the CP1
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-- # Most of the CP0 registers and of course all of the CP1
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-- # External interrupts
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-- # External interrupts
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--
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--
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--### Things implemented but not tested
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--### Things implemented but not tested
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-- # Memory pause input
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-- # Memory pause input
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-- 1.- Load interlocks: the pipeline is stalled for every load instruction, even
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-- 1.- Load interlocks: the pipeline is stalled for every load instruction, even
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-- if the target register is not used in the following instruction. So that
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-- if the target register is not used in the following instruction. So that
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-- every load takes two cycles.
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-- every load takes two cycles.
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-- The interlock logic should check register indices.
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-- The interlock logic should check register indices.
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--
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--
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-- 2.- Invalid instructions trigger trap cause 10 but their side affects are NOT
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-- prevented.
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_arith.all;
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-- IMPORTANT: This attribute is used by Xilinx tools to select how to implement
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-- IMPORTANT: This attribute is used by Xilinx tools to select how to implement
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-- the register bank. If we don't use it, by default XST would infer 2 BRAMs for
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-- the register bank. If we don't use it, by default XST would infer 2 BRAMs for
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-- the 1024-bit 3-port reg bank, which you probably don't want.
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-- the 1024-bit 3-port reg bank, which you probably don't want.
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-- This can take the values {distributed|block}.
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-- This can take the values {distributed|block}.
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attribute ram_style : string;
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attribute ram_style : string;
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attribute ram_style of p1_rbank : signal is "distributed";
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attribute ram_style of p1_rbank : signal is XILINX_REGBANK;
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signal p1_rs, p1_rt : t_word;
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signal p1_rs, p1_rt : t_word;
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signal p1_rs_rbank : t_word;
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signal p1_rs_rbank : t_word;
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signal p1_rt_rbank : t_word;
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signal p1_rt_rbank : t_word;
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signal p1_rbank_forward : t_word;
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signal p1_rbank_forward : t_word;
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Line 553... |
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p1_do_reg_jump <= '1' when p1_op_special='1' and p1_ir_fn(5 downto 1)="00100" else '0';
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p1_do_reg_jump <= '1' when p1_op_special='1' and p1_ir_fn(5 downto 1)="00100" else '0';
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p1_do_zero_ext_imm <= '1' when (p1_ir_op(31 downto 28)="0011") else '0';
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p1_do_zero_ext_imm <= '1' when (p1_ir_op(31 downto 28)="0011") else '0';
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-- Decode input data mux control (LW, LH, LB, LBU, LHU) and load enable
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-- Decode input data mux control (LW, LH, LB, LBU, LHU) and load enable
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p1_do_load <= '1' when p1_ir_op(31 downto 29)="100" and
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p1_do_load <= '1' when
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p2_exception='0'
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p1_ir_op(31 downto 29)="100" and
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p1_ir_op(28 downto 26)/="010" and -- LWL
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p1_ir_op(28 downto 26)/="110" and -- LWR
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p1_ir_op(28 downto 26)/="111" and -- LWR
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p2_exception='0' -- abort load if previous instruction triggered trap
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else '0';
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else '0';
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p1_load_alu_set0 <= '1'
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p1_load_alu_set0 <= '1'
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when p1_op_special='1' and
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when p1_op_special='1' and
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((p1_ir_op(31 downto 29)="000" and p1_ir_op(27 downto 26)="00") or
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((p1_ir_op(31 downto 29)="000" and p1_ir_op(27 downto 26)="00") or
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Line 607... |
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-- ALU input-2 final selection
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-- ALU input-2 final selection
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p1_alu_op2_sel <= p1_alu_op2_sel_set0 or p1_alu_op2_sel_set1;
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p1_alu_op2_sel <= p1_alu_op2_sel_set0 or p1_alu_op2_sel_set1;
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-- Decode store operations
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-- Decode store operations
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p1_do_store <=
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p1_do_store <= '1' when
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'1' when p1_ir_op(31 downto 29)="101" and
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p1_ir_op(31 downto 29)="101" and
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(p1_ir_op(28 downto 26)="000" or -- SB
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p1_ir_op(28 downto 26)="001" or -- SH
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p1_ir_op(28 downto 26)="011") and -- SWH
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p2_exception='0' -- abort when previous instruction triggered exception
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p2_exception='0' -- abort when previous instruction triggered exception
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else '0';
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else '0';
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p1_store_size <= p1_ir_op(27 downto 26);
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p1_store_size <= p1_ir_op(27 downto 26);
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