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-- ion_cpu.vhdl -- MIPS-I(tm) compatible CPU core

-- ion_cpu.vhdl -- MIPS-I(tm) compatible CPU core

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-- project:       ION (http://www.opencores.org/project,ion_cpu)

-- project:       ION (http://www.opencores.org/project,ion_cpu)

-- author:        Jose A. Ruiz (ja_rd@hotmail.com)

-- author:        Jose A. Ruiz (ja_rd@hotmail.com)

-- created:       Jan/11/2011

-- created:       Jan/11/2011

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-- Software placed into the public domain by the author. Use under the terms of

-- Software placed into the public domain by the author. Use under the terms of

-- the GPL.

-- the GPL.

-- Software 'as is' without warranty.  Author liable for nothing.

-- Software 'as is' without warranty.  Author liable for nothing.

--

--

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--### MIPS-I things not implemented

--### MIPS-I things not implemented

--  # Invalid instruction trapping:

--  # Invalid instruction trapping:

--  # Kernel/user status

--  # Kernel/user status

--  # Most of the CP0 registers and of course all of the CP1

--  # Most of the CP0 registers and of course all of the CP1

--  # External interrupts

--  # External interrupts

--

--

--### Things implemented but not tested

--### Things implemented but not tested

--  # Memory pause input

--  # Memory pause input

-- 1.- Load interlocks: the pipeline is stalled for every load instruction, even

-- 1.- Load interlocks: the pipeline is stalled for every load instruction, even

--     if the target register is not used in the following instruction. So that

--     if the target register is not used in the following instruction. So that

--     every load takes two cycles.

--     every load takes two cycles.

--     The interlock logic should check register indices.

--     The interlock logic should check register indices.

--

--

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library ieee;

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_1164.all;

use ieee.std_logic_arith.all;

use ieee.std_logic_arith.all;

-- IMPORTANT: This attribute is used by Xilinx tools to select how to implement

-- IMPORTANT: This attribute is used by Xilinx tools to select how to implement

-- the register bank. If we don't use it, by default XST would infer 2 BRAMs for

-- the register bank. If we don't use it, by default XST would infer 2 BRAMs for

-- the 1024-bit 3-port reg bank, which you probably don't want.

-- the 1024-bit 3-port reg bank, which you probably don't want.

-- This can take the values {distributed|block}.

-- This can take the values {distributed|block}.

attribute ram_style :       string;

attribute ram_style :       string;

signal p1_rs, p1_rt :       t_word;

signal p1_rs, p1_rt :       t_word;

signal p1_rs_rbank :        t_word;

signal p1_rs_rbank :        t_word;

signal p1_rt_rbank :        t_word;

signal p1_rt_rbank :        t_word;

signal p1_rbank_forward :   t_word;

signal p1_rbank_forward :   t_word;

p1_do_reg_jump <= '1' when p1_op_special='1' and p1_ir_fn(5 downto 1)="00100" else '0';

p1_do_reg_jump <= '1' when p1_op_special='1' and p1_ir_fn(5 downto 1)="00100" else '0';

p1_do_zero_ext_imm <= '1' when (p1_ir_op(31 downto 28)="0011") else '0';

p1_do_zero_ext_imm <= '1' when (p1_ir_op(31 downto 28)="0011") else '0';

-- Decode input data mux control (LW, LH, LB, LBU, LHU) and load enable

-- Decode input data mux control (LW, LH, LB, LBU, LHU) and load enable

              else '0';

              else '0';

p1_load_alu_set0 <= '1'

p1_load_alu_set0 <= '1'

    when p1_op_special='1' and

    when p1_op_special='1' and

        ((p1_ir_op(31 downto 29)="000" and p1_ir_op(27 downto 26)="00") or

        ((p1_ir_op(31 downto 29)="000" and p1_ir_op(27 downto 26)="00") or

-- ALU input-2 final selection

-- ALU input-2 final selection

p1_alu_op2_sel <= p1_alu_op2_sel_set0 or p1_alu_op2_sel_set1;

p1_alu_op2_sel <= p1_alu_op2_sel_set0 or p1_alu_op2_sel_set1;

-- Decode store operations

-- Decode store operations

    p2_exception='0'    -- abort when previous instruction triggered exception

    p2_exception='0'    -- abort when previous instruction triggered exception

    else '0';

    else '0';

p1_store_size <= p1_ir_op(27 downto 26);

p1_store_size <= p1_ir_op(27 downto 26);