| Line 266... |
Line 266... |
p0_pc_incremented & "00" when "11",
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p0_pc_incremented & "00" when "11",
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cp0_reg_read when others;
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cp0_reg_read when others;
|
|
|
p1_rbank_we <= '1' when (p2_do_load='1' or p1_load_alu='1' or
|
p1_rbank_we <= '1' when (p2_do_load='1' or p1_load_alu='1' or
|
p1_link='1' or p1_get_cp0='1') and
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p1_link='1' or p1_get_cp0='1') and
|
|
-- If target register is $zero, ignore write
|
p1_rbank_wr_addr/="00000" and
|
p1_rbank_wr_addr/="00000" and
|
|
-- if the cache controller keeps the cpu stopped, do
|
|
-- not writeback
|
|
mem_wait='0' and
|
-- on exception, abort next instruction (by preventing
|
-- on exception, abort next instruction (by preventing
|
-- regbank writeback).
|
-- regbank writeback).
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p2_exception='0'
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p2_exception='0'
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else '0';
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else '0';
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|
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| Line 441... |
Line 445... |
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
end process pc_register;
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end process pc_register;
|
|
|
-- p0_pc_reg holds the same addr as the addr register of the external synchronous
|
-- FIXME we should not output the lowest 2 bits
|
-- memory; what we put on the addr bus is p0_pc_next.
|
|
data_rd_addr <= p1_data_addr(31 downto 0);
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data_rd_addr <= p1_data_addr(31 downto 0);
|
|
|
-- FIXME these two need to pushed behind a register, they are glitch-prone
|
-- FIXME these two need to pushed behind a register, they are glitch-prone
|
data_rd_vma <= p1_do_load and not pipeline_stalled; -- FIXME register
|
data_rd_vma <= p1_do_load and not pipeline_stalled; -- FIXME register
|
code_rd_vma <= not stall_pipeline; -- FIXME register
|
code_rd_vma <= not stall_pipeline; -- FIXME register
|
| Line 818... |
Line 821... |
if stall_pipeline='1' then
|
if stall_pipeline='1' then
|
pipeline_stalled <= '1';
|
pipeline_stalled <= '1';
|
else
|
else
|
pipeline_stalled <= '0';
|
pipeline_stalled <= '0';
|
end if;
|
end if;
|
|
|
|
-- stalls caused by mem_wait and load_interlock are independent and
|
|
-- must not overlap; so when mem_wait='1' the cache stall takes
|
|
-- precedence and the loa interlock must wait.
|
|
if mem_wait='0' then
|
if load_interlock='1' then
|
if load_interlock='1' then
|
pipeline_interlocked <= '1';
|
pipeline_interlocked <= '1';
|
else
|
else
|
pipeline_interlocked <= '0';
|
pipeline_interlocked <= '0';
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
|
end if;
|
end process pipeline_stall_registers;
|
end process pipeline_stall_registers;
|
|
|
-- FIXME make sure this combinational will not have bad glitches
|
-- FIXME make sure this combinational will not have bad glitches
|
stall_pipeline <= mem_wait or load_interlock or p1_muldiv_stall;
|
stall_pipeline <= mem_wait or load_interlock or p1_muldiv_stall;
|
|
|
