| Line 373... |
Line 373... |
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-- main pc mux: jump or continue
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-- main pc mux: jump or continue
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p0_pc_next <=
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p0_pc_next <=
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p0_pc_target when
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p0_pc_target when
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-- We jump on jump instructions whose condition is met...
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-- We jump on jump instructions whose condition is met...
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((p1_jump_type(1)='1' and p0_jump_cond_value='1') or
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((p1_jump_type(1)='1' and p0_jump_cond_value='1' and
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-- ... or on exceptions...
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-- ...except we abort any jump that follows the victim of an exception
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p2_exception='0') or
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-- We jump on exceptions too...
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p1_exception='1')
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p1_exception='1')
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-- ... but only if the pipeline is not stalled
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-- ... but we only jump at all if the pipeline is not stalled
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and stall_pipeline='0'
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and stall_pipeline='0'
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else p0_pc_incremented;
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else p0_pc_incremented;
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pc_register:
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pc_register:
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process(clk)
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process(clk)
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| Line 504... |
Line 506... |
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p1_do_reg_jump <= '1' when p1_op_special='1' and p1_ir_fn(5 downto 1)="00100" else '0';
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p1_do_reg_jump <= '1' when p1_op_special='1' and p1_ir_fn(5 downto 1)="00100" else '0';
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p1_do_zero_ext_imm <= '1' when (p1_ir_op(31 downto 28)="0011") else '0';
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p1_do_zero_ext_imm <= '1' when (p1_ir_op(31 downto 28)="0011") else '0';
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-- Decode input data mux control (LW, LH, LB, LBU, LHU) and load enable
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-- Decode input data mux control (LW, LH, LB, LBU, LHU) and load enable
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p1_do_load <= '1' when p1_ir_op(31 downto 29)="100" else '0';
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p1_do_load <= '1' when p1_ir_op(31 downto 29)="100" and
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p2_exception='0'
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else '0';
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p1_load_alu_set0 <= '1'
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p1_load_alu_set0 <= '1'
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when p1_op_special='1' and
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when p1_op_special='1' and
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((p1_ir_op(31 downto 29)="000" and p1_ir_op(27 downto 26)="00") or
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((p1_ir_op(31 downto 29)="000" and p1_ir_op(27 downto 26)="00") or
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(p1_ir_op(31 downto 29)="000" and p1_ir_op(27 downto 26)="10") or
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(p1_ir_op(31 downto 29)="000" and p1_ir_op(27 downto 26)="10") or
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| Line 623... |
Line 627... |
p1_rbank_rt_hazard <= p0_rbank_rt_hazard;
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p1_rbank_rt_hazard <= p0_rbank_rt_hazard;
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end if;
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end if;
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end if;
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end if;
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end process pipeline_stage1_register;
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end process pipeline_stage1_register;
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-- Stage 2 pipeline register. Involved in memory loads.
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-- Stage 2 pipeline register. Split in two for convenience.
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-- This register deals with two kinds of stalls:
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-- This register deals with two kinds of stalls:
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-- * When the pipeline stalls because of a load interlock, this register is
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-- * When the pipeline stalls because of a load interlock, this register is
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-- allowed to update so that the load operation can complete while the rest of
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-- allowed to update so that the load operation can complete while the rest of
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-- the pipeline is frozen.
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-- the pipeline is frozen.
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-- * When the stall is caused by any other reason, this register freezes with
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-- * When the stall is caused by any other reason, this register freezes with
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-- the rest of the machine.
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-- the rest of the machine.
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pipeline_stage2_register:
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-- Part of stage 2 register that controls load operation
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pipeline_stage2_register_load_control:
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process(clk)
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process(clk)
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begin
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begin
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if clk'event and clk='1' then
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if clk'event and clk='1' then
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if reset='1' then
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-- Clear load control, effectively preventing load, at reset or if
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p2_exception <= '0';
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-- the previous instruction raised an exception.
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if reset='1' or p2_exception='1' then
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p2_do_load <= '0';
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p2_do_load <= '0';
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p2_ld_upper_hword <= '0';
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p2_ld_upper_hword <= '0';
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p2_ld_upper_byte <= '0';
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p2_ld_upper_byte <= '0';
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p2_ld_unsigned <= '0';
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p2_ld_unsigned <= '0';
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p2_load_target <= "00000";
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p2_load_target <= "00000";
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elsif stall_pipeline='0' or load_interlock='1' then
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-- Load signals from previous stage only if there is no pipeline stall
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-- unless the stall is caused by interlock (@note1).
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elsif (stall_pipeline='0' or load_interlock='1') then
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-- Disable reg bank writeback if pipeline is stalled; this prevents
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-- duplicate writes in case the stall is a mem_wait.
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if pipeline_stalled='0' then
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if pipeline_stalled='0' then
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p2_do_load <= p1_do_load;
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p2_do_load <= p1_do_load;
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else
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else
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p2_do_load <= '0';
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p2_do_load <= '0';
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end if;
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end if;
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p2_load_target <= p1_rd_num;
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p2_load_target <= p1_rd_num;
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p2_ld_upper_hword <= p1_ld_upper_hword;
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p2_ld_upper_hword <= p1_ld_upper_hword;
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p2_ld_upper_byte <= p1_ld_upper_byte;
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p2_ld_upper_byte <= p1_ld_upper_byte;
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p2_ld_unsigned <= p1_ld_unsigned;
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p2_ld_unsigned <= p1_ld_unsigned;
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end if;
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end if;
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end process pipeline_stage2_register_load_control;
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-- All the rest of the stage 2 register
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pipeline_stage2_register_others:
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process(clk)
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begin
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if clk'event and clk='1' then
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if reset='1' then
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p2_exception <= '0';
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-- Load signals from previous stage only if there is no pipeline stall
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-- unless the stall is caused by interlock (@note1).
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elsif (stall_pipeline='0' or load_interlock='1') then
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p2_rd_addr <= p1_data_addr(1 downto 0);
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p2_rd_addr <= p1_data_addr(1 downto 0);
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p2_exception <= p1_exception;
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p2_exception <= p1_exception;
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end if;
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end if;
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end if;
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end if;
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end process pipeline_stage2_register;
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end process pipeline_stage2_register_others;
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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-- FIXME stall when needed: mem pause, mdiv pause and load interlock
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-- FIXME stall when needed: mem pause, mdiv pause and load interlock
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