| Line 19... |
Line 19... |
-- # RTE instruction (or ERET)
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-- # RTE instruction (or ERET)
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-- # Most of the CP0 registers and of course all of the CP1
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-- # Most of the CP0 registers and of course all of the CP1
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-- # External interrupts
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-- # External interrupts
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--
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--
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--### Things implemented but not tested
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--### Things implemented but not tested
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-- # Memory pause input -- not tested with a real cache
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-- # Memory pause input -- only tested with stub cache
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--
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--
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--### Things with provisional implementation
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--### Things with provisional implementation
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--
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--
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-- 1.- Load interlocks: the pipeline is stalled for every load instruction, even
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-- 1.- Load interlocks: the pipeline is stalled for every load instruction, even
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-- if the target register is not used in the following instruction. So that
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-- if the target register is not used in the following instruction. So that
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| Line 38... |
Line 38... |
use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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use work.mips_pkg.all;
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use work.mips_pkg.all;
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|
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entity mips_cpu is
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entity mips_cpu is
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generic(
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generic(
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-- Reset vector address minus 4
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RESET_VECTOR_M4 : t_word := RESET_VECTOR_M4;
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-- Trap vector address
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TRAP_VECTOR : t_word := TRAP_VECTOR;
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-- Type of memory to be used for register bank in xilinx HW
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XILINX_REGBANK : string := "distributed" -- {distributed|block}
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XILINX_REGBANK : string := "distributed" -- {distributed|block}
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);
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);
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port(
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port(
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clk : in std_logic;
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clk : in std_logic;
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reset : in std_logic;
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reset : in std_logic;
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| Line 433... |
Line 438... |
pc_register:
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pc_register:
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process(clk)
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process(clk)
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begin
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begin
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if clk'event and clk='1' then
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if clk'event and clk='1' then
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if reset='1' then
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if reset='1' then
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-- reset to 0xffffffff so that 1st fetch addr is 0x00000000
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-- reset to <vector>-4 so that 1st fetch addr is <vector>
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-- FIXME reset vector is hardcoded
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p0_pc_reg <= RESET_VECTOR_M4(31 downto 2);
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p0_pc_reg <= (others => '1');
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else
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else
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-- p0_pc_reg holds the same value as external sync ram addr register
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-- p0_pc_reg holds the same value as external sync ram addr register
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p0_pc_reg <= p0_pc_next;
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p0_pc_reg <= p0_pc_next;
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-- p0_pc_restart = addr saved to EPC on interrupts (@note2)
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-- p0_pc_restart = addr saved to EPC on interrupts (@note2)
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-- It's the addr of the instruction triggering the exception,
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-- It's the addr of the instruction triggering the exception,
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| Line 477... |
Line 481... |
p1_branch_offset <= p1_branch_offset_sex & p1_ir_reg(15 downto 0);
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p1_branch_offset <= p1_branch_offset_sex & p1_ir_reg(15 downto 0);
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-- p0_pc_reg is the addr of the instruction in delay slot
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-- p0_pc_reg is the addr of the instruction in delay slot
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p0_pc_branch <= p0_pc_reg + p1_branch_offset;
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p0_pc_branch <= p0_pc_reg + p1_branch_offset;
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|
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-- decide which jump target is to be used
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-- decide which jump target is to be used
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p0_pc_target <= X"0000003"&"11" when p1_exception='1' else
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p0_pc_target <=
|
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TRAP_VECTOR(31 downto 2) when p1_exception='1' else
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p0_pc_jump when p1_jump_type(0)='1' else
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p0_pc_jump when p1_jump_type(0)='1' else
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p0_pc_branch;
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p0_pc_branch;
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|
|
|
|
--##############################################################################
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--##############################################################################
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| Line 957... |
Line 962... |
-- no need to check for stall cycles when loading these
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-- no need to check for stall cycles when loading these
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if p1_set_cp0='1' then
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if p1_set_cp0='1' then
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-- FIXME check for CP0 reg index
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-- FIXME check for CP0 reg index
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cp0_status <= p1_rs(cp0_status'high downto 0);
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cp0_status <= p1_rs(cp0_status'high downto 0);
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end if;
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end if;
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if p1_exception='1' then
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if p1_exception='1' and pipeline_stalled='0' then
|
cp0_epc <= p0_pc_restart;
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cp0_epc <= p0_pc_restart;
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|
|
if p1_unknown_opcode='1' then
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if p1_unknown_opcode='1' then
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cp0_cause_exc_code <= "01010"; -- bad opcode
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cp0_cause_exc_code <= "01010"; -- bad opcode
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else
|
else
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