| Line 78... |
Line 78... |
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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-- Pipeline stage 0
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-- Pipeline stage 0
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signal p0_pc_reg : t_pc;
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signal p0_pc_reg : t_pc;
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signal p0_pc_restart : t_pc;
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signal p0_pc_incremented : t_pc;
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signal p0_pc_incremented : t_pc;
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signal p0_pc_jump : t_pc;
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signal p0_pc_jump : t_pc;
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signal p0_pc_branch : t_pc;
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signal p0_pc_branch : t_pc;
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signal p0_pc_target : t_pc;
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signal p0_pc_target : t_pc;
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signal p0_pc_next : t_pc;
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signal p0_pc_next : t_pc;
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| Line 392... |
Line 393... |
-- reset to 0xffffffff so that 1st fetch addr is 0x00000000
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-- reset to 0xffffffff so that 1st fetch addr is 0x00000000
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p0_pc_reg <= (others => '1');
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p0_pc_reg <= (others => '1');
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else
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else
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-- p0_pc_reg holds the same value as external sync ram addr register
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-- p0_pc_reg holds the same value as external sync ram addr register
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p0_pc_reg <= p0_pc_next;
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p0_pc_reg <= p0_pc_next;
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-- p0_pc_restart = addr saved to EPC on interrupts (@note2)
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-- It's the addr of the instruction triggering the exception
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-- FIXME handle delay slot case
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if (p1_jump_type="00" or p0_jump_cond_value='0') then
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p0_pc_restart <= p0_pc_reg;
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end if;
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end if;
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end if;
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end if;
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end if;
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end process pc_register;
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end process pc_register;
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-- p0_pc_reg holds the same addr as the addr register of the external synchronous
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-- p0_pc_reg holds the same addr as the addr register of the external synchronous
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| Line 779... |
Line 786... |
if p1_set_cp0='1' then
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if p1_set_cp0='1' then
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-- FIXME check for CP0 reg index
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-- FIXME check for CP0 reg index
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cp0_status <= p1_rs(cp0_status'high downto 0);
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cp0_status <= p1_rs(cp0_status'high downto 0);
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end if;
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end if;
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if p1_exception='1' then
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if p1_exception='1' then
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cp0_epc <= p0_pc_reg;
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cp0_epc <= p0_pc_restart;
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end if;
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end if;
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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