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-- ion_cpu.vhdl -- MIPS-I(tm) compatible CPU core
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-- ion_cpu.vhdl -- MIPS-I(tm) compatible CPU core
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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-- project: ION (http://www.opencores.org/project,ion_cpu)
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-- project: ION (http://www.opencores.org/project,ion_cpu)
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-- author: Jose A. Ruiz (ja_rd@hotmail.com)
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-- author: Jose A. Ruiz (ja_rd@hotmail.com)
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-- created: Jan/11/2011
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-- created: Jan/11/2011
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-- last modified: Jan/31/2011 (ja_rd@hotmail.com)
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-- last modified: Mar/03/2011 (ja_rd@hotmail.com)
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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-- Software placed into the public domain by the author. Use under the terms of
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-- Software placed into the public domain by the author. Use under the terms of
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-- the GPL.
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-- the GPL.
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-- Software 'as is' without warranty. Author liable for nothing.
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-- Software 'as is' without warranty. Author liable for nothing.
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--
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--
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port(
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port(
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clk : in std_logic;
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clk : in std_logic;
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reset : in std_logic;
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reset : in std_logic;
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interrupt : in std_logic;
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interrupt : in std_logic;
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data_rd_addr : out std_logic_vector(31 downto 0);
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data_addr : out std_logic_vector(31 downto 0);
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data_rd : in std_logic_vector(31 downto 0);
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data_rd : in std_logic_vector(31 downto 0);
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data_rd_vma : out std_logic;
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data_rd_vma : out std_logic;
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byte_we : out std_logic_vector(3 downto 0);
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data_wr : out std_logic_vector(31 downto 0);
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code_rd_addr : out std_logic_vector(31 downto 2);
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code_rd_addr : out std_logic_vector(31 downto 2);
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code_rd : in std_logic_vector(31 downto 0);
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code_rd : in std_logic_vector(31 downto 0);
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code_rd_vma : out std_logic;
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code_rd_vma : out std_logic;
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data_wr_addr : out std_logic_vector(31 downto 2);
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byte_we : out std_logic_vector(3 downto 0);
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data_wr : out std_logic_vector(31 downto 0);
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mem_wait : in std_logic
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mem_wait : in std_logic
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);
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);
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end; --entity mips_cpu
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end; --entity mips_cpu
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architecture rtl of mips_cpu is
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architecture rtl of mips_cpu is
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end if;
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end if;
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end if;
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end if;
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end if;
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end if;
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end process pc_register;
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end process pc_register;
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-- FIXME we should not output the lowest 2 bits
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-- Common rd/wr address; lowest 2 bits are output as debugging aid only
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data_rd_addr <= p1_data_addr(31 downto 0);
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data_addr <= p1_data_addr(31 downto 0);
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-- FIXME these two need to pushed behind a register, they are glitch-prone
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-- FIXME these two need to pushed behind a register, they are glitch-prone
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data_rd_vma <= p1_do_load and not pipeline_stalled; -- FIXME register
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data_rd_vma <= p1_do_load and not pipeline_stalled; -- FIXME register
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code_rd_vma <= not stall_pipeline; -- FIXME register
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code_rd_vma <= not stall_pipeline; -- FIXME register
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code_rd_addr <= p0_pc_next;
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code_rd_addr <= p0_pc_next;
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data_wr_addr <= p1_data_addr(31 downto 2);
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-- compute target of J/JR instructions
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-- compute target of J/JR instructions
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p0_pc_jump <= p1_rs(31 downto 2) when p1_do_reg_jump='1' else
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p0_pc_jump <= p1_rs(31 downto 2) when p1_do_reg_jump='1' else
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p0_pc_reg(31 downto 28) & p1_ir_reg(25 downto 0);
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p0_pc_reg(31 downto 28) & p1_ir_reg(25 downto 0);
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