| Line 119... |
Line 119... |
a_neg, b_neg, sum, sign_reg, mode_reg, negate_reg,
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a_neg, b_neg, sum, sign_reg, mode_reg, negate_reg,
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count_reg, aa_reg, bb_reg, upper_reg, lower_reg)
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count_reg, aa_reg, bb_reg, upper_reg, lower_reg)
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variable count : std_logic_vector(2 downto 0);
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variable count : std_logic_vector(2 downto 0);
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begin
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begin
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count := "001";
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count := "001";
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-- @ion Old asynchronous reset converted to synchronous, for consistency
|
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-- (Code indenting mangled by the new 'if' level)
|
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--if reset_in = '1' then
|
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if rising_edge(clk) then
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if reset_in = '1' then
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if reset_in = '1' then
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mode_reg <= '0';
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mode_reg <= '0';
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negate_reg <= '0';
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negate_reg <= '0';
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sign_reg <= '0';
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sign_reg <= '0';
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sign2_reg <= '0';
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sign2_reg <= '0';
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count_reg <= "000000";
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count_reg <= "000000";
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aa_reg <= ZERO;
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aa_reg <= ZERO;
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bb_reg <= ZERO;
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bb_reg <= ZERO;
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upper_reg <= ZERO;
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upper_reg <= ZERO;
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lower_reg <= ZERO;
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lower_reg <= ZERO;
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elsif rising_edge(clk) then
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--elsif rising_edge(clk) then
|
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else
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case mult_func is
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case mult_func is
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when MULT_WRITE_LO =>
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when MULT_WRITE_LO =>
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lower_reg <= a;
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lower_reg <= a;
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negate_reg <= '0';
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negate_reg <= '0';
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when MULT_WRITE_HI =>
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when MULT_WRITE_HI =>
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| Line 227... |
Line 232... |
end if; --count
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end if; --count
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|
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end case;
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end case;
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|
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end if;
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end if;
|
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end if;
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|
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end process;
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end process;
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|
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end; --architecture logic
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end; --architecture logic
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|
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| Line 246... |
Line 252... |
-- as @note1 but with no apparent improvement in synthesis results.
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-- as @note1 but with no apparent improvement in synthesis results.
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--
|
--
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-- @note3 : pause_out active until operation complete
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-- @note3 : pause_out active until operation complete
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-- The original Plasma module allowed the pipeline and the multiplier to run
|
-- The original Plasma module allowed the pipeline and the multiplier to run
|
-- concurrently until the multiplier result was needed, and only then the
|
-- concurrently until the multiplier result was needed, and only then the
|
-- pipeline was stalled.
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-- pipeline was stalled if the mul/div operation had not finished yet.
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-- We want to make sure we can abort a mul/div so for the time being we stall
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-- We want to make sure we can abort a mul/div so for the time being we stall
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-- until the operation is complete.
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-- until the operation is complete.
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-- note that if we later want to change this, the parent module will need
|
-- I *think* that's what the libraries and the toolchain assume anyway.
|
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-- Note that if we later want to change this, the parent module will need
|
-- changes too (logic for p1_muldiv_running).
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-- changes too (logic for p1_muldiv_running).
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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No newline at end of file
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No newline at end of file
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