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-- additional address decoding you may do out of the FPGA (e.g. if you have more
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-- additional address decoding you may do out of the FPGA (e.g. if you have more
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-- than one chip on any data bus) or out of the MCU module (e.g. when you add
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-- than one chip on any data bus) or out of the MCU module (e.g. when you add
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-- new IO registers).
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-- new IO registers).
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-- Please see the module c2sb_demo and mips_mcu for examples of memory decoding.
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-- Please see the module c2sb_demo and mips_mcu for examples of memory decoding.
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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-- Copyright (C) 2010 Jose A. Ruiz
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--
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-- This source file may be used and distributed without
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-- restriction provided that this copyright statement is not
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-- removed from the file and that any derivative work contains
|
|
-- the original copyright notice and the associated disclaimer.
|
|
--
|
|
-- This source file is free software; you can redistribute it
|
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-- and/or modify it under the terms of the GNU Lesser General
|
|
-- Public License as published by the Free Software Foundation;
|
|
-- either version 2.1 of the License, or (at your option) any
|
|
-- later version.
|
|
--
|
|
-- This source is distributed in the hope that it will be
|
|
-- useful, but WITHOUT ANY WARRANTY; without even the implied
|
|
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
|
|
-- PURPOSE. See the GNU Lesser General Public License for more
|
|
-- details.
|
|
--
|
|
-- You should have received a copy of the GNU Lesser General
|
|
-- Public License along with this source; if not, download it
|
|
-- from http://www.opencores.org/lgpl.shtml
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--------------------------------------------------------------------------------
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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