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[/] [ion/] [trunk/] [vhdl/] [tb/] [mips_tb.vhdl] - Diff between revs 205 and 207

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Rev 205 Rev 207
Line 41... Line 41...
-- NOTE: simulation parameters are defined in sim_params_pkg
-- NOTE: simulation parameters are defined in sim_params_pkg
 
 
 
 
-- External SRAM and interface signals -----------------------------------------
-- External SRAM and interface signals -----------------------------------------
 
 
signal sram1 : t_sram := ( others => X"00");
-- Static 16-bit wide RAM modelled as two separate byte-wide arrays foer easy 
signal sram0 : t_sram := ( others => X"00");
-- simulation of byte enables.
 
-- Using shared variables for big memory arrays speeds up simulation a lot;
 
-- see Modelsim 6.3 User Manual, section on 'Modelling Memory'.
 
-- WARNING: I have only tested this construct with Modelsim SE 6.3.
 
shared variable sram1 : t_sram := ( others => X"00");
 
shared variable sram0 : t_sram := ( others => X"00");
 
 
signal sram_chip_addr :     std_logic_vector(SRAM_ADDR_SIZE downto 1);
signal sram_chip_addr :     std_logic_vector(SRAM_ADDR_SIZE downto 1);
signal sram_output :        std_logic_vector(15 downto 0);
signal sram_output :        std_logic_vector(15 downto 0);
 
 
 
 
-- PROM table and interface signals --------------------------------------------
-- PROM table and interface signals --------------------------------------------
 
 
-- We'll simulate a 16-bit-wide static PROM (e.g. a Flash) with some serious
-- We'll simulate a 16-bit-wide static PROM (e.g. a Flash) with some serious
-- cycle time (70 or 90 ns).
-- cycle time (70 or 90 ns).
 
-- FIXME FLASH read cycle time not modelled yet.
signal prom_rd_addr :       t_prom_address;
signal prom_rd_addr :       t_prom_address;
signal prom_output :        std_logic_vector(7 downto 0);
signal prom_output :        std_logic_vector(7 downto 0);
signal prom_oe_n :          std_logic;
signal prom_oe_n :          std_logic;
 
 
signal prom : t_prom := ( PROM_DATA );
-- 8-bit wide FLASH modelled as read only block.
 
-- We don't simulate the actual FLASH chip: no FLASH writes, control regs, etc.
 
shared variable prom : t_prom := ( PROM_DATA );
 
 
 
 
-- I/O devices -----------------------------------------------------------------
-- I/O devices -----------------------------------------------------------------
 
 
signal data_uart :          std_logic_vector(31 downto 0);
signal data_uart :          std_logic_vector(31 downto 0);
Line 214... Line 220...
    begin
    begin
        -- Write cycle
        -- Write cycle
        -- FIXME should add OE\ to write control logic
        -- FIXME should add OE\ to write control logic
        if mpu_sram_byte_we_n'event or mpu_sram_address'event then
        if mpu_sram_byte_we_n'event or mpu_sram_address'event then
            if mpu_sram_byte_we_n(1)='0' then
            if mpu_sram_byte_we_n(1)='0' then
                sram1(conv_integer(unsigned(sram_chip_addr))) <= mpu_sram_data_wr(15 downto  8);
                sram1(conv_integer(unsigned(sram_chip_addr))) := mpu_sram_data_wr(15 downto  8);
            end if;
            end if;
            if mpu_sram_byte_we_n(0)='0' then
            if mpu_sram_byte_we_n(0)='0' then
                sram0(conv_integer(unsigned(sram_chip_addr))) <= mpu_sram_data_wr( 7 downto  0);
                sram0(conv_integer(unsigned(sram_chip_addr))) := mpu_sram_data_wr( 7 downto  0);
            end if;
            end if;
        end if;
        end if;
    end process simulated_sram_write;
    end process simulated_sram_write;
 
 
 
 

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