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-- NOTE: simulation parameters are defined in sim_params_pkg
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-- NOTE: simulation parameters are defined in sim_params_pkg
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-- External SRAM and interface signals -----------------------------------------
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-- External SRAM and interface signals -----------------------------------------
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signal sram1 : t_sram := ( others => X"00");
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-- Static 16-bit wide RAM modelled as two separate byte-wide arrays foer easy
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signal sram0 : t_sram := ( others => X"00");
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-- simulation of byte enables.
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-- Using shared variables for big memory arrays speeds up simulation a lot;
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-- see Modelsim 6.3 User Manual, section on 'Modelling Memory'.
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-- WARNING: I have only tested this construct with Modelsim SE 6.3.
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shared variable sram1 : t_sram := ( others => X"00");
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shared variable sram0 : t_sram := ( others => X"00");
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signal sram_chip_addr : std_logic_vector(SRAM_ADDR_SIZE downto 1);
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signal sram_chip_addr : std_logic_vector(SRAM_ADDR_SIZE downto 1);
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signal sram_output : std_logic_vector(15 downto 0);
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signal sram_output : std_logic_vector(15 downto 0);
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-- PROM table and interface signals --------------------------------------------
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-- PROM table and interface signals --------------------------------------------
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-- We'll simulate a 16-bit-wide static PROM (e.g. a Flash) with some serious
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-- We'll simulate a 16-bit-wide static PROM (e.g. a Flash) with some serious
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-- cycle time (70 or 90 ns).
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-- cycle time (70 or 90 ns).
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-- FIXME FLASH read cycle time not modelled yet.
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signal prom_rd_addr : t_prom_address;
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signal prom_rd_addr : t_prom_address;
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signal prom_output : std_logic_vector(7 downto 0);
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signal prom_output : std_logic_vector(7 downto 0);
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signal prom_oe_n : std_logic;
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signal prom_oe_n : std_logic;
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signal prom : t_prom := ( PROM_DATA );
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-- 8-bit wide FLASH modelled as read only block.
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-- We don't simulate the actual FLASH chip: no FLASH writes, control regs, etc.
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shared variable prom : t_prom := ( PROM_DATA );
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-- I/O devices -----------------------------------------------------------------
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-- I/O devices -----------------------------------------------------------------
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signal data_uart : std_logic_vector(31 downto 0);
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signal data_uart : std_logic_vector(31 downto 0);
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begin
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begin
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-- Write cycle
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-- Write cycle
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-- FIXME should add OE\ to write control logic
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-- FIXME should add OE\ to write control logic
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if mpu_sram_byte_we_n'event or mpu_sram_address'event then
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if mpu_sram_byte_we_n'event or mpu_sram_address'event then
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if mpu_sram_byte_we_n(1)='0' then
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if mpu_sram_byte_we_n(1)='0' then
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sram1(conv_integer(unsigned(sram_chip_addr))) <= mpu_sram_data_wr(15 downto 8);
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sram1(conv_integer(unsigned(sram_chip_addr))) := mpu_sram_data_wr(15 downto 8);
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end if;
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end if;
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if mpu_sram_byte_we_n(0)='0' then
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if mpu_sram_byte_we_n(0)='0' then
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sram0(conv_integer(unsigned(sram_chip_addr))) <= mpu_sram_data_wr( 7 downto 0);
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sram0(conv_integer(unsigned(sram_chip_addr))) := mpu_sram_data_wr( 7 downto 0);
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end if;
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end if;
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end if;
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end if;
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end process simulated_sram_write;
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end process simulated_sram_write;
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