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Line 126... |
subtype t_irq_countdown is std_logic_vector(31 downto 0);
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subtype t_irq_countdown is std_logic_vector(31 downto 0);
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type t_irq_countdown_array is array(0 to 7) of t_irq_countdown;
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type t_irq_countdown_array is array(0 to 7) of t_irq_countdown;
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signal irq_countdown : t_irq_countdown_array;
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signal irq_countdown : t_irq_countdown_array;
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-- Simulated block of 4 read/write, 32-bit I/O registers, used in cache test.
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type t_debug_reg_block is array(0 to 3) of t_word;
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signal debug_reg_block : t_debug_reg_block;
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begin
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begin
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-- UUT instantiation -------------------------------------------------------
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-- UUT instantiation -------------------------------------------------------
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mpu: entity work.mips_mpu
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mpu: entity work.mips_mpu
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Line 258... |
variable uart_data : integer;
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variable uart_data : integer;
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begin
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begin
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if clk'event and clk='1' then
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if clk'event and clk='1' then
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if io_byte_we /= "0000" then
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if io_byte_we /= "0000" then
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if io_wr_addr(31 downto 16)=X"2001" then
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if io_wr_addr(31 downto 16)=X"2001" then
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-- IRQ trigger register block (write only)
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irq_trigger_load <= '1';
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irq_trigger_load <= '1';
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irq_trigger_data <= io_wr_data;
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irq_trigger_data <= io_wr_data;
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irq_trigger_addr <= io_wr_addr(4 downto 2);
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irq_trigger_addr <= io_wr_addr(4 downto 2);
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elsif io_wr_addr(31 downto 12)=X"2000f" then
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-- Debug register block (read/write)
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debug_reg_block(conv_integer(unsigned(io_wr_addr(3 downto 2)))) <= io_wr_data;
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else
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else
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irq_trigger_load <= '0';
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irq_trigger_load <= '0';
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end if;
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end if;
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else
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else
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irq_trigger_load <= '0';
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irq_trigger_load <= '0';
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end if;
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end if;
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end if;
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end if;
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end process simulated_io;
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end process simulated_io;
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-- The only readable i/o is the debug reg block. We simulate an asynchronous
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-- read port (a mux).
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io_rd_data <= debug_reg_block(conv_integer(unsigned(io_rd_addr(3 downto 2))));
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-- Simulate IRQs -----------------------------------------------------------
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-- Simulate IRQs -----------------------------------------------------------
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irq_trigger_registers:
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irq_trigger_registers:
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process(clk)
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process(clk)
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variable index : integer range 0 to 7;
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variable index : integer range 0 to 7;
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begin
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begin
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