| Line 56... |
Line 56... |
negate_reg_lo : std_logic;
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negate_reg_lo : std_logic;
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mdiv_count_reg : std_logic_vector(5 downto 0);
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mdiv_count_reg : std_logic_vector(5 downto 0);
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prev_count_reg : std_logic_vector(5 downto 0);
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prev_count_reg : std_logic_vector(5 downto 0);
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data_rd_vma : std_logic;
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data_rd_vma : std_logic;
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p1_rbank_we : std_logic;
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code_rd_vma : std_logic;
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code_rd_vma : std_logic;
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data_byte_we : std_logic_vector(3 downto 0);
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data_byte_we : std_logic_vector(3 downto 0);
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present_data_wr_addr : t_word;
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present_data_wr_addr : t_word;
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present_data_wr : t_word;
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present_data_wr : t_word;
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| Line 75... |
Line 76... |
word_loaded : t_word;
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word_loaded : t_word;
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mdiv_address : t_word;
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mdiv_address : t_word;
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mdiv_pending : boolean;
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mdiv_pending : boolean;
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exception : std_logic;
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exception_pc : t_word;
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data_rd_address : t_word;
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data_rd_address : t_word;
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load : std_logic;
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load : std_logic;
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read_pending : boolean;
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read_pending : boolean;
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write_pending : boolean;
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write_pending : boolean;
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debug : t_word;
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-- Log trigger --------------------------------------------------
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-- Log trigger --------------------------------------------------
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-- Enable logging after fetching from a given address -----------
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-- Enable logging after fetching from a given address -----------
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log_trigger_address : t_word;
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log_trigger_address : t_word;
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log_triggered : boolean;
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log_triggered : boolean;
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| Line 125... |
Line 130... |
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-- This is the address of the opcode that triggered the changed we're
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-- This is the address of the opcode that triggered the changed we're
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-- about to log
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-- about to log
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full_pc := info.pc_m(k);
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full_pc := info.pc_m(k);
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-- Log activity only at the 1st cycle of each instruction
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if info.code_rd_vma='1' then
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-- Log register changes -------------------------------------
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ri := X"00";
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for i in 0 to 31 loop
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if info.prev_rbank(i)/=info.rbank(i)
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and info.prev_rbank(i)(0)/='U' then
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if info.log_triggered then
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print(l_file, "("& hstr(full_pc)& ") "&
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"["& hstr(ri)& "]="& hstr(info.rbank(i)));
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end if;
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end if;
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ri := ri + 1;
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end loop;
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-- Log memory writes ----------------------------------------
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-- Log memory writes ----------------------------------------
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if info.write_pending then
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if info.write_pending then
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if conv_integer(info.pending_data_wr_pc) <= conv_integer(full_pc) then
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ri := X"0" & info.pending_data_wr_we;
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ri := X"0" & info.pending_data_wr_we;
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temp := info.pending_data_wr;
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temp := info.pending_data_wr;
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if info.pending_data_wr_we(3)='0' then
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if info.pending_data_wr_we(3)='0' then
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temp := temp and X"00ffffff";
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temp := temp and X"00ffffff";
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| Line 165... |
Line 154... |
print(l_file, "("& hstr(info.pending_data_wr_pc) &") ["&
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print(l_file, "("& hstr(info.pending_data_wr_pc) &") ["&
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hstr(info.pending_data_wr_addr) &"] |"&
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hstr(info.pending_data_wr_addr) &"] |"&
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hstr(ri)& "|="&
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hstr(ri)& "|="&
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hstr(temp)& " WR" );
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hstr(temp)& " WR" );
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end if;
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end if;
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info.debug <= info.pending_data_wr_pc;
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info.write_pending <= false;
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info.write_pending <= false;
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end if;
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end if;
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end if;
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-- Log register bank activity.
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-- NOTE: in previous versions we used to do this only at the 1st cycle of
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--- instructions, mistakenly. Reg changes need to be logged as soon as
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-- they happen.
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if true then --info.code_rd_vma='1' then
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-- Log memory reads ------------------------------------------
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-- Log register changes -------------------------------------
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if info.read_pending and info.load='1' then
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ri := X"00";
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for i in 0 to 31 loop
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if info.prev_rbank(i)/=info.rbank(i)
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and info.prev_rbank(i)(0)/='U' then
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if info.log_triggered then
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if info.log_triggered then
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print(l_file, "("& hstr(info.pc_m(1)) &") ["&
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print(l_file, "("& hstr(info.pc_m(k-0))& ") "&
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hstr(info.pending_data_rd_addr) &"] <"&
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"["& hstr(ri)& "]="& hstr(info.rbank(i)));
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"**"& ">="&
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hstr(info.word_loaded)& " RD" ); -- FIXME
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end if;
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end if;
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info.read_pending <= false;
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end if;
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end if;
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ri := ri + 1;
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end loop;
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-- Log aux register changes ---------------------------------
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-- Log aux register changes ---------------------------------
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if info.prev_lo /= info.reg_lo and info.prev_lo(0)/='U' then
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if info.prev_lo /= info.reg_lo and info.prev_lo(0)/='U' then
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-- Adjust opcode PC when LO came from the mul module
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-- Adjust opcode PC when LO came from the mul module
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if info.mdiv_pending then
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if info.mdiv_pending then
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temp2 := info.mdiv_address;
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temp2 := info.mdiv_address;
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info.mdiv_pending <= false;
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info.mdiv_pending <= false;
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else
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else
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temp2 := info.pc_m(k-1);
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temp2 := info.pc_m(k-2);
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end if;
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end if;
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-- we're observing the value of reg_lo, but the mult core
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-- we're observing the value of reg_lo, but the mult core
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-- will output the negated value in some cases. We
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-- will output the negated value in some cases. We
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-- have to mimic that behavior.
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-- have to mimic that behavior.
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| Line 212... |
Line 210... |
-- Adjust opcode PC when HI came from the mul module
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-- Adjust opcode PC when HI came from the mul module
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if info.mdiv_pending then
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if info.mdiv_pending then
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temp2 := info.mdiv_address;
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temp2 := info.mdiv_address;
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info.mdiv_pending <= false;
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info.mdiv_pending <= false;
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else
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else
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temp2 := info.pc_m(k-1);
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temp2 := info.pc_m(k-2);
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end if;
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end if;
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if info.log_triggered then
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if info.log_triggered then
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print(l_file, "("& hstr(temp2)& ") [HI]="& hstr(info.reg_hi));
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print(l_file, "("& hstr(temp2)& ") [HI]="& hstr(info.reg_hi));
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end if;
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end if;
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end if;
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end if;
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if info.prev_epc /= info.cp0_epc and info.cp0_epc(31)/='U' then
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if info.prev_epc /= info.cp0_epc and info.cp0_epc(31)/='U' then
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temp := info.cp0_epc & "00";
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temp := info.cp0_epc & "00";
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if info.log_triggered then
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if info.log_triggered then
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print(l_file, "("& hstr(info.pc_m(k-1))& ") [EP]="& hstr(temp));
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-- The instruction that caused the EP change is the last
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-- recorded trap/syscall exception.
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print(l_file, "("& hstr(info.exception_pc)& ") [EP]="& hstr(temp));
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end if;
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end if;
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info.prev_epc <= info.cp0_epc;
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info.prev_epc <= info.cp0_epc;
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end if;
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end if;
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-- Save present cycle info to compare the next cycle --------
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-- Save present cycle info to compare the next cycle --------
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info.prev_rbank <= info.rbank;
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info.prev_rbank <= info.rbank;
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info.prev_hi <= info.reg_hi;
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info.prev_hi <= info.reg_hi;
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info.prev_lo <= info.reg_lo;
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info.prev_lo <= info.reg_lo;
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--info.pc_m(3) <= info.pc_m(2);
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--info.pc_m(2) <= info.pc_m(1);
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--info.pc_m(1) <= info.pc_m(0);
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--info.pc_m(0) <= info.present_code_rd_addr & "00";
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end if;
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-- Update instruction address table only at the 1st cycle of each
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-- instruction.
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if info.code_rd_vma='1' then
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info.pc_m(3) <= info.pc_m(2);
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info.pc_m(3) <= info.pc_m(2);
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info.pc_m(2) <= info.pc_m(1);
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info.pc_m(2) <= info.pc_m(1);
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info.pc_m(1) <= info.pc_m(0);
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info.pc_m(1) <= info.pc_m(0);
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info.pc_m(0) <= info.present_code_rd_addr & "00";
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info.pc_m(0) <= info.present_code_rd_addr & "00";
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end if;
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-- Log memory reads ------------------------------------------
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if info.read_pending and info.load='1' and info.p1_rbank_we='1' then
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if info.log_triggered then
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print(l_file, "("& hstr(info.pc_m(1)) &") ["&
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hstr(info.pending_data_rd_addr) &"] <"&
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"**"& ">="&
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hstr(info.word_loaded)& " RD" );
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end if;
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info.read_pending <= false;
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end if;
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if info.exception='1' then
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info.exception_pc <= info.pc_m(1);
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end if;
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end if;
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if info.data_byte_we/="0000" then
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if info.data_byte_we/="0000" then
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info.write_pending <= true;
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info.write_pending <= true;
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info.pending_data_wr_we <= info.data_byte_we;
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info.pending_data_wr_we <= info.data_byte_we;
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| Line 281... |
Line 305... |
init_signal_spy("/"&entity_name&"/mult_div/lower_reg", signal_name&".reg_lo", 0, -1);
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init_signal_spy("/"&entity_name&"/mult_div/lower_reg", signal_name&".reg_lo", 0, -1);
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init_signal_spy("/"&entity_name&"/mult_div/negate_reg", signal_name&".negate_reg_lo", 0, -1);
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init_signal_spy("/"&entity_name&"/mult_div/negate_reg", signal_name&".negate_reg_lo", 0, -1);
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init_signal_spy("/"&entity_name&"/mult_div/count_reg", signal_name&".mdiv_count_reg", 0, -1);
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init_signal_spy("/"&entity_name&"/mult_div/count_reg", signal_name&".mdiv_count_reg", 0, -1);
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init_signal_spy("/"&entity_name&"/cp0_epc", signal_name&".cp0_epc", 0, -1);
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init_signal_spy("/"&entity_name&"/cp0_epc", signal_name&".cp0_epc", 0, -1);
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init_signal_spy("/"&entity_name&"/data_rd_vma", signal_name&".data_rd_vma", 0, -1);
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init_signal_spy("/"&entity_name&"/data_rd_vma", signal_name&".data_rd_vma", 0, -1);
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init_signal_spy("/"&entity_name&"/p1_rbank_we", signal_name&".p1_rbank_we", 0, -1);
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init_signal_spy("/"&entity_name&"/code_rd_vma", signal_name&".code_rd_vma", 0, -1);
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init_signal_spy("/"&entity_name&"/code_rd_vma", signal_name&".code_rd_vma", 0, -1);
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init_signal_spy("/"&entity_name&"/p2_do_load", signal_name&".load", 0, -1);
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init_signal_spy("/"&entity_name&"/p2_do_load", signal_name&".load", 0, -1);
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init_signal_spy("/"&entity_name&"/data_addr", signal_name&".present_data_wr_addr", 0, -1);
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init_signal_spy("/"&entity_name&"/data_addr", signal_name&".present_data_wr_addr", 0, -1);
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init_signal_spy("/"&entity_name&"/data_wr", signal_name&".present_data_wr", 0, -1);
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init_signal_spy("/"&entity_name&"/data_wr", signal_name&".present_data_wr", 0, -1);
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init_signal_spy("/"&entity_name&"/byte_we", signal_name&".data_byte_we", 0, -1);
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init_signal_spy("/"&entity_name&"/byte_we", signal_name&".data_byte_we", 0, -1);
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init_signal_spy("/"&entity_name&"/p2_data_word_rd", signal_name&".word_loaded", 0, -1);
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init_signal_spy("/"&entity_name&"/p2_data_word_rd", signal_name&".word_loaded", 0, -1);
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init_signal_spy("/"&entity_name&"/data_addr", signal_name&".present_data_rd_addr", 0, -1);
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init_signal_spy("/"&entity_name&"/data_addr", signal_name&".present_data_rd_addr", 0, -1);
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init_signal_spy("/"&entity_name&"/p1_exception", signal_name&".exception", 0, -1);
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while done='0' loop
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while done='0' loop
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wait until clk'event and clk='1';
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wait until clk'event and clk='1';
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if reset='1' then
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if reset='1' then
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-- FIXME should use real reset vector here
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-- FIXME should use real reset vector here
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| Line 300... |
Line 326... |
-- By default logging is DISABLED by triggering with an impossible
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-- By default logging is DISABLED by triggering with an impossible
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-- fetch address. Logging must be enabled from outside by
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-- fetch address. Logging must be enabled from outside by
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-- setting log_trigger_address to a suitable value.
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-- setting log_trigger_address to a suitable value.
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info.log_trigger_address <= trigger_addr;
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info.log_trigger_address <= trigger_addr;
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info.log_triggered <= false;
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info.log_triggered <= false;
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info.debug <= (others => '0');
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else
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else
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log_cpu_status(info, l_file);
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log_cpu_status(info, l_file);
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end if;
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end if;
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end loop;
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end loop;
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