| Line 1... |
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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-- mips_tb_pkg.vhdl -- Functions and data for the simulation test benches.
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-- mips_tb_pkg.vhdl -- Functions and data for the simulation test benches.
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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-- Most of this file deals with the 'simulation log': the CPU execution history
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-- Most of this file deals with the 'simulation log': the CPU execution history
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-- is logged to a text file for easy comparison to a similaro log written by the
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-- is logged to a text file for easy comparison to a similar log written by the
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-- software simulator. This is meant as a debugging tool and is explained to
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-- software simulator. This is meant as a debugging tool and is explained in
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-- some detail in the project doc.
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-- some detail in the project doc.
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-- It is used as a verification tool at least while no better verification test
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-- It is used as a verification tool at least while no other verification test
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-- bench exists.
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-- bench exists.
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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-- FIXME Console logging code should be here too
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-- FIXME Console logging code should be here too
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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-- WARNING:
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-- WARNING:
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-- This package contains arguably the worst code of the project; in order
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-- This package contains arguably the worst code of the project; in order
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-- to expedite things, a number of trial-and-error hacks have been performed on
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-- to expedite things, a number of trial-and-error hacks have been performed on
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-- the code below. Mostly, the adjustment of the displayed PC.
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-- the code below. Mostly, the adjustment of the displayed PC.
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-- This is just the kind of hdl you don't want prospective employers to see :)
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-- This is just the kind of hdl you don't want prospective employers to see :)
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-- At least the synthesis tools never get to see it, it's simulation only.
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--
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--
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-- The problem is: each change in the CPU state is logged in a text line, in
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-- The problem is: each change in the CPU state is logged in a text line, in
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-- which the address of the instruction that caused the change is included.
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-- which the address of the instruction that caused the change is included.
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-- From outside the CPU it is not always trivial to find out what instruction
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-- From outside the CPU it is not always trivial to find out what instruction
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-- caused what change (pipeline delays, cache stalls, etc.).
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-- caused what change (pipeline delays, cache stalls, etc.).
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-- I think the logging rules should be pretty stable now but I might have to
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-- I think the logging rules should be pretty stable now but I might have to
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-- tweak them again as the cache implementation changes. Eventually I aim to
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-- tweak them again as the cache implementation changes. Eventually I aim to
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-- make this code fully independent of the cache implementation; it should
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-- make this code fully independent of the cache implementation; it should
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-- only depend on the cpu. I will do this step by step, as I do all the rest.
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-- only depend on the cpu. I will do this step by step, as I do all the rest.
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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-- NOTES (tagged in the code as @note1, etc.):
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--
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-- note1:
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-- The multiplier LO/HI register change logging has been disabled (commented
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-- out) until fixed (it fails in code sample 'adventure').
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-- Please note it's the LOGGING that fails, not the instruction.
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--
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--------------------------------------------------------------------------------
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library ieee,modelsim_lib;
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library ieee,modelsim_lib;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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| Line 46... |
Line 55... |
rbank : t_rbank;
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rbank : t_rbank;
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prev_rbank : t_rbank;
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prev_rbank : t_rbank;
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cp0_epc : t_pc;
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cp0_epc : t_pc;
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prev_epc : t_pc;
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prev_epc : t_pc;
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cp0_status : std_logic_vector(5 downto 0);
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cp0_cache_control : std_logic_vector(1 downto 0);
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prev_status : t_word;
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p1_set_cp0 : std_logic;
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pc_mtc0 : t_word;
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pc_m : t_pc_queue;
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pc_m : t_pc_queue;
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reg_hi, reg_lo : t_word;
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reg_hi, reg_lo : t_word;
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prev_hi, prev_lo : t_word;
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prev_hi, prev_lo : t_word;
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| Line 114... |
Line 128... |
file l_file : TEXT) is
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file l_file : TEXT) is
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variable i : integer;
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variable i : integer;
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variable ri : std_logic_vector(7 downto 0);
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variable ri : std_logic_vector(7 downto 0);
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variable full_pc, temp, temp2 : t_word;
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variable full_pc, temp, temp2 : t_word;
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variable k : integer := 2;
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variable k : integer := 2;
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variable log_trap_status : boolean := false;
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begin
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begin
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-- Trigger logging if the CPU fetches from trigger address
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-- Trigger logging if the CPU fetches from trigger address
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if (info.log_trigger_address(31 downto 2) = info.present_code_rd_addr) and
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if (info.log_trigger_address(31 downto 2) = info.present_code_rd_addr) and
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info.code_rd_vma='1' then
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info.code_rd_vma='1' then
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| Line 179... |
Line 194... |
end if;
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end if;
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ri := ri + 1;
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ri := ri + 1;
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end loop;
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end loop;
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-- Log aux register changes ---------------------------------
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-- Log aux register changes ---------------------------------
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-- Mult/div module, register LO
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if info.prev_lo /= info.reg_lo and info.prev_lo(0)/='U' then
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if info.prev_lo /= info.reg_lo and info.prev_lo(0)/='U' then
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-- Adjust opcode PC when LO came from the mul module
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-- Adjust opcode PC when LO came from the mul module
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if info.mdiv_pending then
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if info.mdiv_pending then
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temp2 := info.mdiv_address;
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temp2 := info.mdiv_address;
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info.mdiv_pending <= false;
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info.mdiv_pending <= false;
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| Line 196... |
Line 213... |
if info.negate_reg_lo='1' then
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if info.negate_reg_lo='1' then
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-- negate reg_lo before displaying
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-- negate reg_lo before displaying
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temp := not info.reg_lo;
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temp := not info.reg_lo;
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temp := temp + 1;
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temp := temp + 1;
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if info.log_triggered then
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if info.log_triggered then
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print(l_file, "("& hstr(temp2)& ") [LO]="& hstr(temp));
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-- FIXME removed temporarily until fixed (@note1)
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--print(l_file, "("& hstr(temp2)& ") [LO]="& hstr(temp));
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end if;
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end if;
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else
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else
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if info.log_triggered then
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if info.log_triggered then
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print(l_file, "("& hstr(temp2)& ") [LO]="& hstr(info.reg_lo));
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-- FIXME removed temporarily until fixed (@note1)
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--print(l_file, "("& hstr(temp2)& ") [LO]="& hstr(info.reg_lo));
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end if;
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end if;
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end if;
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end if;
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end if;
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end if;
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-- Mult/div module, register HI
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if info.prev_hi /= info.reg_hi and info.prev_hi(0)/='U' then
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if info.prev_hi /= info.reg_hi and info.prev_hi(0)/='U' then
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-- Adjust opcode PC when HI came from the mul module
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-- Adjust opcode PC when HI came from the mul module
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if info.mdiv_pending then
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if info.mdiv_pending then
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temp2 := info.mdiv_address;
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temp2 := info.mdiv_address;
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info.mdiv_pending <= false;
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info.mdiv_pending <= false;
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else
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else
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temp2 := info.pc_m(k-2);
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temp2 := info.pc_m(k-2);
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end if;
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end if;
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|
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if info.log_triggered then
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if info.log_triggered then
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print(l_file, "("& hstr(temp2)& ") [HI]="& hstr(info.reg_hi));
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-- FIXME removed temporarily until fixed (@note1)
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--print(l_file, "("& hstr(temp2)& ") [HI]="& hstr(info.reg_hi));
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end if;
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end if;
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end if;
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end if;
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|
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-- CP0, register EPC
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if info.prev_epc /= info.cp0_epc and info.cp0_epc(31)/='U' then
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if info.prev_epc /= info.cp0_epc and info.cp0_epc(31)/='U' then
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temp := info.cp0_epc & "00";
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temp := info.cp0_epc & "00";
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if info.log_triggered then
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if info.log_triggered then
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-- The instruction that caused the EP change is the last
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-- The instruction that caused the EP change is the last
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-- recorded trap/syscall exception.
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-- recorded trap/syscall exception.
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print(l_file, "("& hstr(info.exception_pc)& ") [EP]="& hstr(temp));
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print(l_file, "("& hstr(info.exception_pc)& ") [EP]="& hstr(temp));
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end if;
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end if;
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info.prev_epc <= info.cp0_epc;
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info.prev_epc <= info.cp0_epc;
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|
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log_trap_status := true;
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else
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log_trap_status := false;
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end if;
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|
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-- CP0, register SR
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|
|
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-- If SR changed by mtc0 instruction, get the mtc0 address
|
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if info.p1_set_cp0='1' and info.cp0_status(1)='1' then
|
|
info.pc_mtc0 <= info.pc_m(k-1);
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end if;
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|
|
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-- Build SR from separate CPU signals
|
|
temp := X"000" & "00" & info.cp0_cache_control &
|
|
X"00" & "00" & info.cp0_status;
|
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if info.prev_status /= temp and info.cp0_status(0)/='U' then
|
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if info.log_triggered then
|
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if log_trap_status then
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-- The instruction that caused the SR change is the last
|
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-- recorded trap/syscall exception.
|
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print(l_file, "("& hstr(info.exception_pc)& ") [SR]="& hstr(temp));
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else
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-- The instruction that caused the change is mtc0
|
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print(l_file, "("& hstr(info.pc_mtc0)& ") [SR]="& hstr(temp));
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end if;
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end if;
|
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info.prev_status <= temp;
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end if;
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end if;
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|
|
|
|
-- Save present cycle info to compare the next cycle --------
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-- Save present cycle info to compare the next cycle --------
|
info.prev_rbank <= info.rbank;
|
info.prev_rbank <= info.rbank;
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info.prev_hi <= info.reg_hi;
|
info.prev_hi <= info.reg_hi;
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info.prev_lo <= info.reg_lo;
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info.prev_lo <= info.reg_lo;
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|
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--info.pc_m(3) <= info.pc_m(2);
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--info.pc_m(2) <= info.pc_m(1);
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--info.pc_m(1) <= info.pc_m(0);
|
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--info.pc_m(0) <= info.present_code_rd_addr & "00";
|
|
|
|
end if;
|
end if;
|
|
|
-- Update instruction address table only at the 1st cycle of each
|
-- Update instruction address table only at the 1st cycle of each
|
-- instruction.
|
-- instruction.
|
if info.code_rd_vma='1' then
|
if info.code_rd_vma='1' then
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| Line 304... |
Line 350... |
init_signal_spy("/"&entity_name&"/mult_div/upper_reg", signal_name&".reg_hi", 0, -1);
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init_signal_spy("/"&entity_name&"/mult_div/upper_reg", signal_name&".reg_hi", 0, -1);
|
init_signal_spy("/"&entity_name&"/mult_div/lower_reg", signal_name&".reg_lo", 0, -1);
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init_signal_spy("/"&entity_name&"/mult_div/lower_reg", signal_name&".reg_lo", 0, -1);
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init_signal_spy("/"&entity_name&"/mult_div/negate_reg", signal_name&".negate_reg_lo", 0, -1);
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init_signal_spy("/"&entity_name&"/mult_div/negate_reg", signal_name&".negate_reg_lo", 0, -1);
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init_signal_spy("/"&entity_name&"/mult_div/count_reg", signal_name&".mdiv_count_reg", 0, -1);
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init_signal_spy("/"&entity_name&"/mult_div/count_reg", signal_name&".mdiv_count_reg", 0, -1);
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init_signal_spy("/"&entity_name&"/cp0_epc", signal_name&".cp0_epc", 0, -1);
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init_signal_spy("/"&entity_name&"/cp0_epc", signal_name&".cp0_epc", 0, -1);
|
|
init_signal_spy("/"&entity_name&"/cp0_status", signal_name&".cp0_status", 0, -1);
|
|
init_signal_spy("/"&entity_name&"/p1_set_cp0", signal_name&".p1_set_cp0", 0, -1);
|
|
init_signal_spy("/"&entity_name&"/cp0_cache_control", signal_name&".cp0_cache_control", 0, -1);
|
init_signal_spy("/"&entity_name&"/data_rd_vma", signal_name&".data_rd_vma", 0, -1);
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init_signal_spy("/"&entity_name&"/data_rd_vma", signal_name&".data_rd_vma", 0, -1);
|
init_signal_spy("/"&entity_name&"/p1_rbank_we", signal_name&".p1_rbank_we", 0, -1);
|
init_signal_spy("/"&entity_name&"/p1_rbank_we", signal_name&".p1_rbank_we", 0, -1);
|
init_signal_spy("/"&entity_name&"/code_rd_vma", signal_name&".code_rd_vma", 0, -1);
|
init_signal_spy("/"&entity_name&"/code_rd_vma", signal_name&".code_rd_vma", 0, -1);
|
init_signal_spy("/"&entity_name&"/p2_do_load", signal_name&".load", 0, -1);
|
init_signal_spy("/"&entity_name&"/p2_do_load", signal_name&".load", 0, -1);
|
init_signal_spy("/"&entity_name&"/data_addr", signal_name&".present_data_wr_addr", 0, -1);
|
init_signal_spy("/"&entity_name&"/data_addr", signal_name&".present_data_wr_addr", 0, -1);
|
