| Line 59... |
Line 59... |
prev_epc : t_pc;
|
prev_epc : t_pc;
|
cp0_status : std_logic_vector(5 downto 0);
|
cp0_status : std_logic_vector(5 downto 0);
|
cp0_cache_control : std_logic_vector(1 downto 0);
|
cp0_cache_control : std_logic_vector(1 downto 0);
|
prev_status : t_word;
|
prev_status : t_word;
|
p1_set_cp0 : std_logic;
|
p1_set_cp0 : std_logic;
|
|
p1_rfe : std_logic;
|
pc_mtc0 : t_word;
|
pc_mtc0 : t_word;
|
|
|
pc_m : t_pc_queue;
|
pc_m : t_pc_queue;
|
|
|
reg_hi, reg_lo : t_word;
|
reg_hi, reg_lo : t_word;
|
| Line 258... |
Line 259... |
end if;
|
end if;
|
|
|
-- CP0, register SR
|
-- CP0, register SR
|
|
|
-- If SR changed by mtc0 instruction, get the mtc0 address
|
-- If SR changed by mtc0 instruction, get the mtc0 address
|
if info.p1_set_cp0='1' and info.cp0_status(1)='1' then
|
if (info.p1_set_cp0='1' or info.p1_rfe='1') and info.cp0_status(1)='1' then
|
info.pc_mtc0 <= info.pc_m(k-1);
|
info.pc_mtc0 <= info.pc_m(k-1);
|
end if;
|
end if;
|
|
|
-- Build SR from separate CPU signals
|
-- Build SR from separate CPU signals
|
temp := X"000" & "00" & info.cp0_cache_control &
|
temp := X"000" & "00" & info.cp0_cache_control &
|
| Line 352... |
Line 353... |
init_signal_spy("/"&entity_name&"/mult_div/negate_reg", signal_name&".negate_reg_lo", 0, -1);
|
init_signal_spy("/"&entity_name&"/mult_div/negate_reg", signal_name&".negate_reg_lo", 0, -1);
|
init_signal_spy("/"&entity_name&"/mult_div/count_reg", signal_name&".mdiv_count_reg", 0, -1);
|
init_signal_spy("/"&entity_name&"/mult_div/count_reg", signal_name&".mdiv_count_reg", 0, -1);
|
init_signal_spy("/"&entity_name&"/cp0_epc", signal_name&".cp0_epc", 0, -1);
|
init_signal_spy("/"&entity_name&"/cp0_epc", signal_name&".cp0_epc", 0, -1);
|
init_signal_spy("/"&entity_name&"/cp0_status", signal_name&".cp0_status", 0, -1);
|
init_signal_spy("/"&entity_name&"/cp0_status", signal_name&".cp0_status", 0, -1);
|
init_signal_spy("/"&entity_name&"/p1_set_cp0", signal_name&".p1_set_cp0", 0, -1);
|
init_signal_spy("/"&entity_name&"/p1_set_cp0", signal_name&".p1_set_cp0", 0, -1);
|
|
init_signal_spy("/"&entity_name&"/p1_rfe", signal_name&".p1_rfe", 0, -1);
|
init_signal_spy("/"&entity_name&"/cp0_cache_control", signal_name&".cp0_cache_control", 0, -1);
|
init_signal_spy("/"&entity_name&"/cp0_cache_control", signal_name&".cp0_cache_control", 0, -1);
|
init_signal_spy("/"&entity_name&"/data_rd_vma", signal_name&".data_rd_vma", 0, -1);
|
init_signal_spy("/"&entity_name&"/data_rd_vma", signal_name&".data_rd_vma", 0, -1);
|
init_signal_spy("/"&entity_name&"/p1_rbank_we", signal_name&".p1_rbank_we", 0, -1);
|
init_signal_spy("/"&entity_name&"/p1_rbank_we", signal_name&".p1_rbank_we", 0, -1);
|
init_signal_spy("/"&entity_name&"/code_rd_vma", signal_name&".code_rd_vma", 0, -1);
|
init_signal_spy("/"&entity_name&"/code_rd_vma", signal_name&".code_rd_vma", 0, -1);
|
init_signal_spy("/"&entity_name&"/p2_do_load", signal_name&".load", 0, -1);
|
init_signal_spy("/"&entity_name&"/p2_do_load", signal_name&".load", 0, -1);
|
