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use work.txt_util.all;
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use work.txt_util.all;
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package mips_tb_pkg is
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package mips_tb_pkg is
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-- Maximum line size of for console output log. Lines longer than this will be
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-- truncated.
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constant CONSOLE_LOG_LINE_SIZE : integer := 1024*4;
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type t_pc_queue is array(0 to 3) of t_word;
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type t_pc_queue is array(0 to 3) of t_word;
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type t_log_info is record
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type t_log_info is record
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rbank : t_rbank;
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rbank : t_rbank;
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prev_rbank : t_rbank;
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prev_rbank : t_rbank;
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Line 93... |
pending_data_wr : t_word;
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pending_data_wr : t_word;
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pending_data_wr_we : std_logic_vector(3 downto 0);
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pending_data_wr_we : std_logic_vector(3 downto 0);
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word_loaded : t_word;
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word_loaded : t_word;
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uart_tx : std_logic;
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io_wr_data : t_word;
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mdiv_address : t_word;
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mdiv_address : t_word;
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mdiv_pending : boolean;
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mdiv_pending : boolean;
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exception : std_logic;
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exception : std_logic;
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exception_pc : t_word;
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exception_pc : t_word;
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Line 109... |
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read_pending : boolean;
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read_pending : boolean;
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write_pending : boolean;
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write_pending : boolean;
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debug : t_word;
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debug : t_word;
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-- Console log line buffer --------------------------------------
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con_line_buf : string(1 to CONSOLE_LOG_LINE_SIZE);
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con_line_ix : integer;
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-- Log trigger --------------------------------------------------
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-- Log trigger --------------------------------------------------
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-- Enable logging after fetching from a given address -----------
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-- Enable logging after fetching from a given address -----------
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log_trigger_address : t_word;
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log_trigger_address : t_word;
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log_triggered : boolean;
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log_triggered : boolean;
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end record t_log_info;
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end record t_log_info;
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procedure log_cpu_activity(
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procedure log_cpu_activity(
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signal clk : in std_logic;
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signal clk : in std_logic;
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signal reset : in std_logic;
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signal reset : in std_logic;
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signal done : in std_logic;
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signal done : in std_logic;
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entity_name : string;
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mcu_entity : string;
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cpu_name : string;
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signal info : inout t_log_info;
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signal info : inout t_log_info;
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signal_name : string;
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signal_name : string;
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trigger_addr : in t_word;
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trigger_addr : in t_word;
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file l_file : TEXT);
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file l_file : TEXT;
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file con_file : TEXT);
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end package;
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end package;
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package body mips_tb_pkg is
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package body mips_tb_pkg is
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procedure log_cpu_status(
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procedure log_cpu_status(
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signal info : inout t_log_info;
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signal info : inout t_log_info;
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file l_file : TEXT) is
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file l_file : TEXT;
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file con_file : TEXT) is
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variable i : integer;
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variable i : integer;
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variable ri : std_logic_vector(7 downto 0);
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variable ri : std_logic_vector(7 downto 0);
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variable full_pc, temp, temp2 : t_word;
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variable full_pc, temp, temp2 : t_word;
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variable k : integer := 2;
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variable k : integer := 2;
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variable log_trap_status : boolean := false;
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variable log_trap_status : boolean := false;
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variable uart_data : integer;
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begin
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begin
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-- Trigger logging if the CPU fetches from trigger address
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-- Trigger logging if the CPU fetches from trigger address
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if (info.log_trigger_address(31 downto 2) = info.present_code_rd_addr) and
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if (info.log_trigger_address(31 downto 2) = info.present_code_rd_addr) and
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info.code_rd_vma='1' then
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info.code_rd_vma='1' then
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Line 348... |
info.mdiv_pending <= true;
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info.mdiv_pending <= true;
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end if;
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end if;
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info.prev_count_reg <= info.mdiv_count_reg;
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info.prev_count_reg <= info.mdiv_count_reg;
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-- Log data sent to UART ---------------------------------------------------
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-- TX data may come from the high or low byte (opcodes.s
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-- uses high byte, no_op.c uses low)
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if info.uart_tx = '1' then
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uart_data := conv_integer(unsigned(info.io_wr_data(7 downto 0)));
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-- UART TX data goes to output after a bit of line-buffering
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-- and editing
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if uart_data = 10 then
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-- CR received: print output string and clear it
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print(con_file, info.con_line_buf(1 to info.con_line_ix));
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info.con_line_ix <= 1;
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for i in 1 to info.con_line_buf'high loop
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info.con_line_buf(i) <= ' ';
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end loop;
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elsif uart_data = 13 then
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-- ignore LF
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else
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-- append char to output string
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if info.con_line_ix < info.con_line_buf'high then
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info.con_line_buf(info.con_line_ix) <= character'val(uart_data);
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info.con_line_ix <= info.con_line_ix + 1;
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end if;
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end if;
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end if;
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end procedure log_cpu_status;
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end procedure log_cpu_status;
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procedure log_cpu_activity(
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procedure log_cpu_activity(
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signal clk : in std_logic;
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signal clk : in std_logic;
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signal reset : in std_logic;
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signal reset : in std_logic;
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signal done : in std_logic;
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signal done : in std_logic;
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entity_name : string;
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mcu_entity : string;
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cpu_name : string;
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signal info : inout t_log_info;
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signal info : inout t_log_info;
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signal_name : string;
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signal_name : string;
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trigger_addr : in t_word;
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trigger_addr : in t_word;
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file l_file : TEXT) is
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file l_file : TEXT;
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file con_file : TEXT) is
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begin
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begin
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init_signal_spy("/"&entity_name&"/p1_rbank", signal_name&".rbank", 0, -1);
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init_signal_spy("/"&mcu_entity&"/"&cpu_name&"/p1_rbank", signal_name&".rbank", 0, -1);
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init_signal_spy("/"&entity_name&"/code_rd_addr", signal_name&".present_code_rd_addr", 0, -1);
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init_signal_spy("/"&mcu_entity&"/"&cpu_name&"/code_rd_addr", signal_name&".present_code_rd_addr", 0, -1);
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init_signal_spy("/"&entity_name&"/mult_div/upper_reg", signal_name&".reg_hi", 0, -1);
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init_signal_spy("/"&mcu_entity&"/"&cpu_name&"/mult_div/upper_reg", signal_name&".reg_hi", 0, -1);
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init_signal_spy("/"&entity_name&"/mult_div/lower_reg", signal_name&".reg_lo", 0, -1);
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init_signal_spy("/"&mcu_entity&"/"&cpu_name&"/mult_div/lower_reg", signal_name&".reg_lo", 0, -1);
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init_signal_spy("/"&entity_name&"/mult_div/negate_reg", signal_name&".negate_reg_lo", 0, -1);
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init_signal_spy("/"&mcu_entity&"/"&cpu_name&"/mult_div/negate_reg", signal_name&".negate_reg_lo", 0, -1);
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init_signal_spy("/"&entity_name&"/mult_div/count_reg", signal_name&".mdiv_count_reg", 0, -1);
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init_signal_spy("/"&mcu_entity&"/"&cpu_name&"/mult_div/count_reg", signal_name&".mdiv_count_reg", 0, -1);
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init_signal_spy("/"&entity_name&"/cp0_epc", signal_name&".cp0_epc", 0, -1);
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init_signal_spy("/"&mcu_entity&"/"&cpu_name&"/cp0_epc", signal_name&".cp0_epc", 0, -1);
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init_signal_spy("/"&entity_name&"/cp0_status", signal_name&".cp0_status", 0, -1);
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init_signal_spy("/"&mcu_entity&"/"&cpu_name&"/cp0_status", signal_name&".cp0_status", 0, -1);
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init_signal_spy("/"&entity_name&"/p1_set_cp0", signal_name&".p1_set_cp0", 0, -1);
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init_signal_spy("/"&mcu_entity&"/"&cpu_name&"/p1_set_cp0", signal_name&".p1_set_cp0", 0, -1);
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init_signal_spy("/"&entity_name&"/p1_rfe", signal_name&".p1_rfe", 0, -1);
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init_signal_spy("/"&mcu_entity&"/"&cpu_name&"/p1_rfe", signal_name&".p1_rfe", 0, -1);
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init_signal_spy("/"&entity_name&"/cp0_cache_control", signal_name&".cp0_cache_control", 0, -1);
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init_signal_spy("/"&mcu_entity&"/"&cpu_name&"/cp0_cache_control", signal_name&".cp0_cache_control", 0, -1);
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init_signal_spy("/"&entity_name&"/data_rd_vma", signal_name&".data_rd_vma", 0, -1);
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init_signal_spy("/"&mcu_entity&"/"&cpu_name&"/data_rd_vma", signal_name&".data_rd_vma", 0, -1);
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init_signal_spy("/"&entity_name&"/p1_rbank_we", signal_name&".p1_rbank_we", 0, -1);
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init_signal_spy("/"&mcu_entity&"/"&cpu_name&"/p1_rbank_we", signal_name&".p1_rbank_we", 0, -1);
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init_signal_spy("/"&entity_name&"/code_rd_vma", signal_name&".code_rd_vma", 0, -1);
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init_signal_spy("/"&mcu_entity&"/"&cpu_name&"/code_rd_vma", signal_name&".code_rd_vma", 0, -1);
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init_signal_spy("/"&entity_name&"/p2_do_load", signal_name&".load", 0, -1);
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init_signal_spy("/"&mcu_entity&"/"&cpu_name&"/p2_do_load", signal_name&".load", 0, -1);
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init_signal_spy("/"&entity_name&"/data_addr", signal_name&".present_data_wr_addr", 0, -1);
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init_signal_spy("/"&mcu_entity&"/"&cpu_name&"/data_addr", signal_name&".present_data_wr_addr", 0, -1);
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init_signal_spy("/"&entity_name&"/data_wr", signal_name&".present_data_wr", 0, -1);
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init_signal_spy("/"&mcu_entity&"/"&cpu_name&"/data_wr", signal_name&".present_data_wr", 0, -1);
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init_signal_spy("/"&entity_name&"/byte_we", signal_name&".data_byte_we", 0, -1);
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init_signal_spy("/"&mcu_entity&"/"&cpu_name&"/byte_we", signal_name&".data_byte_we", 0, -1);
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init_signal_spy("/"&entity_name&"/p2_data_word_rd", signal_name&".word_loaded", 0, -1);
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init_signal_spy("/"&mcu_entity&"/"&cpu_name&"/p2_data_word_rd", signal_name&".word_loaded", 0, -1);
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init_signal_spy("/"&entity_name&"/data_addr", signal_name&".present_data_rd_addr", 0, -1);
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init_signal_spy("/"&mcu_entity&"/"&cpu_name&"/data_addr", signal_name&".present_data_rd_addr", 0, -1);
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init_signal_spy("/"&entity_name&"/p1_exception", signal_name&".exception", 0, -1);
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init_signal_spy("/"&mcu_entity&"/"&cpu_name&"/p1_exception", signal_name&".exception", 0, -1);
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init_signal_spy("/"&mcu_entity&"/uart_write", signal_name&".uart_tx", 0, -1);
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init_signal_spy("/"&mcu_entity&"/mpu_io_wr_data", signal_name&".io_wr_data", 0, -1);
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-- We force both 'rdy' uart outputs to speed up the simulation (since the
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-- UART operation is not simulated, just logged).
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signal_force("/"&mcu_entity&"/uart_tx_rdy", "1", 0 ms, freeze, -1 ms, 0);
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signal_force("/"&mcu_entity&"/uart_rx_rdy", "1", 0 ms, freeze, -1 ms, 0);
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-- And we force the UART RX data to a predictable value until we implement
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-- UART RX simulation, eventually.
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signal_force("/"&mcu_entity&"/uart_data_rx", "00000000", 0 ms, freeze, -1 ms, 0);
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while done='0' loop
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while done='0' loop
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wait until clk'event and clk='1';
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wait until clk'event and clk='1';
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if reset='1' then
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if reset='1' then
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-- FIXME should use real reset vector here
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-- FIXME should use real reset vector here
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| Line 378... |
Line 435... |
-- fetch address. Logging must be enabled from outside by
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-- fetch address. Logging must be enabled from outside by
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-- setting log_trigger_address to a suitable value.
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-- setting log_trigger_address to a suitable value.
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info.log_trigger_address <= trigger_addr;
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info.log_trigger_address <= trigger_addr;
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info.log_triggered <= false;
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info.log_triggered <= false;
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info.debug <= (others => '0');
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info.debug <= (others => '0');
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info.con_line_ix <= 1; -- uart log line buffer is empty
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else
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else
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log_cpu_status(info, l_file);
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log_cpu_status(info, l_file, con_file);
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end if;
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end if;
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end loop;
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end loop;
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end procedure log_cpu_activity;
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end procedure log_cpu_activity;
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