| Line 59... |
Line 59... |
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data_rd_vma : std_logic;
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data_rd_vma : std_logic;
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code_rd_vma : std_logic;
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code_rd_vma : std_logic;
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data_byte_we : std_logic_vector(3 downto 0);
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data_byte_we : std_logic_vector(3 downto 0);
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|
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present_data_wr_addr : t_pc;
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present_data_wr_addr : t_word;
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present_data_wr : t_word;
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present_data_wr : t_word;
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present_data_rd_addr : t_word;
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present_data_rd_addr : t_word;
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present_code_rd_addr : t_pc;
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present_code_rd_addr : t_pc;
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|
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pending_data_rd_addr : t_word;
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pending_data_rd_addr : t_word;
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| Line 244... |
Line 244... |
end if;
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end if;
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|
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if info.data_byte_we/="0000" then
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if info.data_byte_we/="0000" then
|
info.write_pending <= true;
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info.write_pending <= true;
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info.pending_data_wr_we <= info.data_byte_we;
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info.pending_data_wr_we <= info.data_byte_we;
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info.pending_data_wr_addr <= info.present_data_wr_addr & "00";
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info.pending_data_wr_addr <= info.present_data_wr_addr;
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info.pending_data_wr_pc <= info.pc_m(k-1);
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info.pending_data_wr_pc <= info.pc_m(k-1);
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info.pending_data_wr <= info.present_data_wr;
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info.pending_data_wr <= info.present_data_wr;
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end if;
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end if;
|
|
|
if info.data_rd_vma='1' then
|
if info.data_rd_vma='1' then
|
| Line 283... |
Line 283... |
init_signal_spy("/"&entity_name&"/mult_div/count_reg", signal_name&".mdiv_count_reg", 0, -1);
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init_signal_spy("/"&entity_name&"/mult_div/count_reg", signal_name&".mdiv_count_reg", 0, -1);
|
init_signal_spy("/"&entity_name&"/cp0_epc", signal_name&".cp0_epc", 0, -1);
|
init_signal_spy("/"&entity_name&"/cp0_epc", signal_name&".cp0_epc", 0, -1);
|
init_signal_spy("/"&entity_name&"/data_rd_vma", signal_name&".data_rd_vma", 0, -1);
|
init_signal_spy("/"&entity_name&"/data_rd_vma", signal_name&".data_rd_vma", 0, -1);
|
init_signal_spy("/"&entity_name&"/code_rd_vma", signal_name&".code_rd_vma", 0, -1);
|
init_signal_spy("/"&entity_name&"/code_rd_vma", signal_name&".code_rd_vma", 0, -1);
|
init_signal_spy("/"&entity_name&"/p2_do_load", signal_name&".load", 0, -1);
|
init_signal_spy("/"&entity_name&"/p2_do_load", signal_name&".load", 0, -1);
|
init_signal_spy("/"&entity_name&"/data_wr_addr", signal_name&".present_data_wr_addr", 0, -1);
|
init_signal_spy("/"&entity_name&"/data_addr", signal_name&".present_data_wr_addr", 0, -1);
|
init_signal_spy("/"&entity_name&"/data_wr", signal_name&".present_data_wr", 0, -1);
|
init_signal_spy("/"&entity_name&"/data_wr", signal_name&".present_data_wr", 0, -1);
|
init_signal_spy("/"&entity_name&"/byte_we", signal_name&".data_byte_we", 0, -1);
|
init_signal_spy("/"&entity_name&"/byte_we", signal_name&".data_byte_we", 0, -1);
|
init_signal_spy("/"&entity_name&"/p2_data_word_rd", signal_name&".word_loaded", 0, -1);
|
init_signal_spy("/"&entity_name&"/p2_data_word_rd", signal_name&".word_loaded", 0, -1);
|
init_signal_spy("/"&entity_name&"/data_rd_addr", signal_name&".present_data_rd_addr", 0, -1);
|
init_signal_spy("/"&entity_name&"/data_addr", signal_name&".present_data_rd_addr", 0, -1);
|
|
|
while done='0' loop
|
while done='0' loop
|
wait until clk'event and clk='1';
|
wait until clk'event and clk='1';
|
if reset='1' then
|
if reset='1' then
|
-- FIXME should use real reset vector here
|
-- FIXME should use real reset vector here
|
