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`timescale 1ns / 1ps
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`timescale 1ns / 1ps
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`default_nettype none
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//////////////////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Company:
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// Engineer: Sebastien Riou
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// Engineer: Sebastien Riou
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//
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//
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// Create Date: 23:57:02 08/31/2010
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// Create Date: 23:57:02 08/31/2010
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// Additional Comments:
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// Additional Comments:
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//
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//
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//////////////////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////////////////
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module Counter(
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module Counter(
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output reg [WIDTH-1:0] counter,
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output reg [WIDTH-1:0] counter,
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output earlyMatch,
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output wire earlyMatch,
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output reg match,
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output reg match,
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output dividedClk,
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output wire dividedClk,
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input [DIVIDER_WIDTH-1:0] divider, // clock divide factor
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input wire [DIVIDER_WIDTH-1:0] divider, // clock divide factor
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input [WIDTH-1:0] compare,
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input wire [WIDTH-1:0] compare,
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input inc,
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input wire inc,
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input clear,
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input wire clear,
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input [WIDTH_INIT-1:0] initVal,
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input wire [WIDTH_INIT-1:0] initVal,
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input clk,
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input wire clk,
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input nReset
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input wire nReset
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);
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);
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//parameters to override
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//parameters to override
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parameter DIVIDER_WIDTH = 16;
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parameter DIVIDER_WIDTH = 16;
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parameter WIDTH = 8;
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parameter WIDTH = 8;
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