| Line 1... |
Line 1... |
/*
|
/*
|
Author: Sebastien Riou (acapola)
|
Author: Sebastien Riou (acapola)
|
Creation date: 19:57:35 10/31/2010
|
Creation date: 19:57:35 10/31/2010
|
|
|
$LastChangedDate: 2011-01-29 13:16:17 +0100 (Sat, 29 Jan 2011) $
|
$LastChangedDate: 2011-02-13 16:20:10 +0100 (Sun, 13 Feb 2011) $
|
$LastChangedBy: acapola $
|
$LastChangedBy: acapola $
|
$LastChangedRevision: 11 $
|
$LastChangedRevision: 15 $
|
$HeadURL: file:///svn/iso7816_3_master/iso7816_3_master/trunk/sources/HalfDuplexUartIf.v $
|
$HeadURL: file:///svn/iso7816_3_master/iso7816_3_master/trunk/sources/HalfDuplexUartIf.v $
|
|
|
This file is under the BSD licence:
|
This file is under the BSD licence:
|
Copyright (c) 2011, Sebastien Riou
|
Copyright (c) 2011, Sebastien Riou
|
|
|
| Line 41... |
Line 41... |
input wire clk,
|
input wire clk,
|
input wire [DIVIDER_WIDTH-1:0] clkPerCycle,
|
input wire [DIVIDER_WIDTH-1:0] clkPerCycle,
|
input wire [7:0] dataIn,
|
input wire [7:0] dataIn,
|
input wire nWeDataIn,
|
input wire nWeDataIn,
|
input wire [CLOCK_PER_BIT_WIDTH-1:0] clocksPerBit,
|
input wire [CLOCK_PER_BIT_WIDTH-1:0] clocksPerBit,
|
|
input wire stopBit2,//0: 1 stop bit, 1: 2 stop bits
|
|
input wire oddParity, //if 1, parity bit is such that data+parity have an odd number of 1
|
|
input wire msbFirst, //if 1, bits order is: startBit, b7, b6, b5...b0, parity
|
output wire [7:0] dataOut,
|
output wire [7:0] dataOut,
|
input wire nCsDataOut,
|
input wire nCsDataOut,
|
output wire [7:0] statusOut,
|
output wire [7:0] statusOut,
|
input wire nCsStatusOut,
|
input wire nCsStatusOut,
|
input wire serialIn,
|
input wire serialIn,
|
| Line 55... |
Line 58... |
|
|
reg [7:0] dataReg;
|
reg [7:0] dataReg;
|
|
|
// Inputs
|
// Inputs
|
wire [7:0] txData;
|
wire [7:0] txData;
|
//wire [12:0] clocksPerBit;
|
|
wire stopBit2=1;
|
|
wire oddParity=0; //if 1, parity bit is such that data+parity have an odd number of 1
|
|
wire msbFirst=0; //if 1, bits will be send in the order startBit, b7, b6, b5...b0, parity
|
|
reg txPending;
|
reg txPending;
|
wire ackFlags;
|
wire ackFlags;
|
|
|
// Outputs
|
// Outputs
|
wire [7:0] rxData;
|
wire [7:0] rxData;
|
| Line 79... |
Line 78... |
wire rxFlagsSet = dataOutReadyFlag | overrunErrorFlag | frameErrorFlag;
|
wire rxFlagsSet = dataOutReadyFlag | overrunErrorFlag | frameErrorFlag;
|
reg bufferFull;
|
reg bufferFull;
|
reg [1:0] flagsReg;
|
reg [1:0] flagsReg;
|
|
|
assign txData = dataReg;
|
assign txData = dataReg;
|
//assign clocksPerBit = 7;
|
|
|
|
assign dataOut=dataReg;
|
assign dataOut=dataReg;
|
assign statusOut[7:0]={txRun, txPending, rxRun, rxStartBit, isTx, flagsReg, bufferFull};
|
assign statusOut[7:0]={txRun, txPending, rxRun, rxStartBit, isTx, flagsReg, bufferFull};
|
|
|
reg waitTxFull0;//internal reg for managing bufferFull bit in Tx
|
reg waitTxFull0;//internal reg for managing bufferFull bit in Tx
|
