URL https://opencores.org/ocsvn/iso7816_3_master/iso7816_3_master/trunk

Subversion Repositories iso7816_3_master

[/] [iso7816_3_master/] [trunk/] [sources/] [HalfDuplexUartIf.v] - Diff between revs 2 and 3

Rev 2	Rev 3
Line 28...	Line 28...
`input nCsDataOut,`	`input nCsDataOut,`
`output [7:0] statusOut,`	`output [7:0] statusOut,`
`input nCsStatusOut,`	`input nCsStatusOut,`
`input serialIn,`	`input serialIn,`
`output serialOut,`	`output serialOut,`
`output isTx,`
`output comClk`	`output comClk`
`);`	`);`
`//parameters to override`	`//parameters to override`
`parameter DIVIDER_WIDTH = 1;`	`parameter DIVIDER_WIDTH = 1;`

Line 55...	Line 54...
`wire txRun;`	`wire txRun;`
`wire endOfRx;`	`wire endOfRx;`
`wire rxRun;`	`wire rxRun;`
`wire rxStartBit;`	`wire rxStartBit;`
`wire txFull;`	`wire txFull;`
`//wire isTx;`	`wire isTx;`

`wire rxFlagsSet = dataOutReadyFlag \| overrunErrorFlag \| frameErrorFlag;`	`wire rxFlagsSet = dataOutReadyFlag \| overrunErrorFlag \| frameErrorFlag;`
`reg bufferFull;`	`reg bufferFull;`
`reg [1:0] flagsReg;`	`reg [1:0] flagsReg;`

Line 117...	Line 116...
`.rxStartBit(rxStartBit),`	`.rxStartBit(rxStartBit),`
`.txFull(txFull),`	`.txFull(txFull),`
`.isTx(isTx),`	`.isTx(isTx),`
`.serialIn(serialIn),`	`.serialIn(serialIn),`
`.serialOut(serialOut),`	`.serialOut(serialOut),`
	`.comClk(comClk),`
`.txData(txData),`	`.txData(txData),`
`.clocksPerBit(clocksPerBit),`	`.clocksPerBit(clocksPerBit),`
`.stopBit2(stopBit2),`	`.stopBit2(stopBit2),`
`.oddParity(oddParity),`	`.oddParity(oddParity),`
`.msbFirst(msbFirst),`	`.msbFirst(msbFirst),`