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`timescale 1ns / 1ps
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`timescale 1ns / 1ps
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`default_nettype none
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//////////////////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Company:
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// Engineer:
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// Engineer:
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//
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//
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// Create Date: 19:57:35 10/31/2010
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// Create Date: 19:57:35 10/31/2010
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// Revision 0.01 - File Created
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// Revision 0.01 - File Created
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// Additional Comments:
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// Additional Comments:
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//
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//
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//////////////////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////////////////
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module HalfDuplexUartIf(
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module HalfDuplexUartIf(
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input nReset,
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input wire nReset,
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input clk,
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input wire clk,
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input [DIVIDER_WIDTH-1:0] clkPerCycle,
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input wire [DIVIDER_WIDTH-1:0] clkPerCycle,
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input [7:0] dataIn,
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input wire [7:0] dataIn,
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input nWeDataIn,
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input wire nWeDataIn,
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output [7:0] dataOut,
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output wire [7:0] dataOut,
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input nCsDataOut,
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input wire nCsDataOut,
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output [7:0] statusOut,
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output wire [7:0] statusOut,
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input nCsStatusOut,
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input wire nCsStatusOut,
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input serialIn,
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input wire serialIn,
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output serialOut,
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output wire serialOut,
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output comClk
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output wire comClk
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);
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);
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//parameters to override
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//parameters to override
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parameter DIVIDER_WIDTH = 1;
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parameter DIVIDER_WIDTH = 1;
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reg [7:0] dataReg;
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reg [7:0] dataReg;
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