| Line 23... |
Line 23... |
input wire nReset,
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input wire nReset,
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input wire clk,
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input wire clk,
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input wire [DIVIDER_WIDTH-1:0] clkPerCycle,
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input wire [DIVIDER_WIDTH-1:0] clkPerCycle,
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input wire [7:0] dataIn,
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input wire [7:0] dataIn,
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input wire nWeDataIn,
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input wire nWeDataIn,
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input wire [CLOCK_PER_BIT_WIDTH-1:0] clocksPerBit,
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output wire [7:0] dataOut,
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output wire [7:0] dataOut,
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input wire nCsDataOut,
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input wire nCsDataOut,
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output wire [7:0] statusOut,
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output wire [7:0] statusOut,
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input wire nCsStatusOut,
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input wire nCsStatusOut,
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input wire serialIn,
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input wire serialIn,
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output wire serialOut,
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output wire serialOut,
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output wire comClk
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output wire comClk
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);
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);
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//parameters to override
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//parameters to override
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parameter DIVIDER_WIDTH = 1;
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parameter DIVIDER_WIDTH = 1;
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parameter CLOCK_PER_BIT_WIDTH = 13; //allow to support default speed of ISO7816
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reg [7:0] dataReg;
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reg [7:0] dataReg;
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// Inputs
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// Inputs
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wire [7:0] txData;
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wire [7:0] txData;
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wire [12:0] clocksPerBit;
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//wire [12:0] clocksPerBit;
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wire stopBit2=1;
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wire stopBit2=1;
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wire oddParity=0; //if 1, parity bit is such that data+parity have an odd number of 1
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wire oddParity=0; //if 1, parity bit is such that data+parity have an odd number of 1
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wire msbFirst=0; //if 1, bits will be send in the order startBit, b7, b6, b5...b0, parity
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wire msbFirst=0; //if 1, bits will be send in the order startBit, b7, b6, b5...b0, parity
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reg txPending;
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reg txPending;
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wire ackFlags;
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wire ackFlags;
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| Line 62... |
Line 64... |
wire rxFlagsSet = dataOutReadyFlag | overrunErrorFlag | frameErrorFlag;
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wire rxFlagsSet = dataOutReadyFlag | overrunErrorFlag | frameErrorFlag;
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reg bufferFull;
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reg bufferFull;
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reg [1:0] flagsReg;
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reg [1:0] flagsReg;
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assign txData = dataReg;
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assign txData = dataReg;
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assign clocksPerBit = 7;
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//assign clocksPerBit = 7;
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assign dataOut=dataReg;
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assign dataOut=dataReg;
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assign statusOut[7:0]={txRun, txPending, rxRun, rxStartBit, isTx, flagsReg, bufferFull};
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assign statusOut[7:0]={txRun, txPending, rxRun, rxStartBit, isTx, flagsReg, bufferFull};
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reg waitTxFull0;//internal reg for managing bufferFull bit in Tx
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reg waitTxFull0;//internal reg for managing bufferFull bit in Tx
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| Line 103... |
Line 105... |
waitTxFull0 <= txFull;
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waitTxFull0 <= txFull;
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end
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end
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end
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end
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end
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end
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BasicHalfDuplexUart #(.DIVIDER_WIDTH(DIVIDER_WIDTH))
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BasicHalfDuplexUart #(
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.DIVIDER_WIDTH(DIVIDER_WIDTH),
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.CLOCK_PER_BIT_WIDTH(CLOCK_PER_BIT_WIDTH)
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)
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uart (
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uart (
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.rxData(rxData),
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.rxData(rxData),
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.overrunErrorFlag(overrunErrorFlag),
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.overrunErrorFlag(overrunErrorFlag),
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.dataOutReadyFlag(dataOutReadyFlag),
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.dataOutReadyFlag(dataOutReadyFlag),
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.frameErrorFlag(frameErrorFlag),
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.frameErrorFlag(frameErrorFlag),
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