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/*
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/*
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Author: Sebastien Riou (acapola)
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Author: Sebastien Riou (acapola)
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Creation date: 17:16:40 01/09/2011
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Creation date: 17:16:40 01/09/2011
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$LastChangedDate: 2011-01-29 13:16:17 +0100 (Sat, 29 Jan 2011) $
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$LastChangedDate: 2011-02-13 16:20:10 +0100 (Sun, 13 Feb 2011) $
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$LastChangedBy: acapola $
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$LastChangedBy: acapola $
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$LastChangedRevision: 11 $
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$LastChangedRevision: 15 $
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$HeadURL: file:///svn/iso7816_3_master/iso7816_3_master/trunk/sources/Iso7816_3_Master.v $
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$HeadURL: file:///svn/iso7816_3_master/iso7816_3_master/trunk/sources/Iso7816_3_Master.v $
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This file is under the BSD licence:
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This file is under the BSD licence:
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Copyright (c) 2011, Sebastien Riou
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Copyright (c) 2011, Sebastien Riou
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input wire startActivation,//Starts activation sequence
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input wire startActivation,//Starts activation sequence
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input wire startDeactivation,//Starts deactivation sequence
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input wire startDeactivation,//Starts deactivation sequence
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input wire [7:0] dataIn,
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input wire [7:0] dataIn,
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input wire nWeDataIn,
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input wire nWeDataIn,
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input wire [12:0] cyclesPerEtu,
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input wire [12:0] cyclesPerEtu,
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output wire [7:0] dataOut,
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output reg [7:0] dataOut,
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input wire nCsDataOut,
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input wire nCsDataOut,
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output wire [7:0] statusOut,
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output wire [7:0] statusOut,
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input wire nCsStatusOut,
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input wire nCsStatusOut,
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output reg isActivated,//set to high by activation sequence, set to low by deactivation sequence
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output reg isActivated,//set to high by activation sequence, set to low by deactivation sequence
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output wire useIndirectConvention,
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output wire useIndirectConvention,
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wire serialOut;
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wire serialOut;
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assign isoSio = isTx ? serialOut : 1'bz;
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assign isoSio = isTx ? serialOut : 1'bz;
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pullup(isoSio);
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pullup(isoSio);
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wire comClk;
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wire comClk;
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wire stopBit2=1'b1;//0: 1 stop bit, 1: 2 stop bits
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wire msbFirst = useIndirectConvention;//if 1, bits order is: startBit, b7, b6, b5...b0, parity
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wire oddParity = 1'b0;//if 1, parity bit is such that data+parity have an odd number of 1
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wire sioHighValue = ~useIndirectConvention;//apply only to data bits
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wire [7:0] uart_dataOut;
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wire [7:0] uart_dataIn = sioHighValue ? dataIn : ~dataIn;
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always @(*) dataOut = sioHighValue ? uart_dataOut : ~uart_dataOut;
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HalfDuplexUartIf #(
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HalfDuplexUartIf #(
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.DIVIDER_WIDTH(1'b1),
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.DIVIDER_WIDTH(1'b1),
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.CLOCK_PER_BIT_WIDTH(4'd13)
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.CLOCK_PER_BIT_WIDTH(4'd13)
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)
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)
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uart (
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uart (
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.nReset(nReset),
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.nReset(nReset),
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.clk(clk),
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.clk(clk),
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.clkPerCycle(1'b0),
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.clkPerCycle(1'b0),
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.dataIn(dataIn),
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.dataIn(uart_dataIn),
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.nWeDataIn(nWeDataIn),
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.nWeDataIn(nWeDataIn),
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.clocksPerBit(cyclesPerEtu),
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.clocksPerBit(cyclesPerEtu),
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.dataOut(dataOut),
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.stopBit2(stopBit2),
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.oddParity(oddParity),
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.msbFirst(msbFirst),
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.dataOut(uart_dataOut),
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.nCsDataOut(nCsDataOut),
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.nCsDataOut(nCsDataOut),
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.statusOut(statusOut),
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.statusOut(statusOut),
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.nCsStatusOut(nCsStatusOut),
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.nCsStatusOut(nCsStatusOut),
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.serialIn(isoSio),
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.serialIn(isoSio),
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.serialOut(serialOut),
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.serialOut(serialOut),
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isActivated <= 1'b0;
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isActivated <= 1'b0;
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end else if(isActivated) begin
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end else if(isActivated) begin
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if(waitTs) begin
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if(waitTs) begin
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if(statusOut[0]) begin
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if(statusOut[0]) begin
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waitTs<=1'b0;
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waitTs<=1'b0;
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ts<=dataOut;
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case(dataOut)
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8'h3B: ts<=dataOut;
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8'h03: ts<=8'h3F;
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default: ts<=dataOut;
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endcase
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end
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end
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resetCnt<=resetCnt+1;
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resetCnt<=resetCnt+1;
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end
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end
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if(startDeactivation) begin
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if(startDeactivation) begin
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isoVdd <= 1'b0;
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isoVdd <= 1'b0;
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