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/*
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/*
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Author: Sebastien Riou (acapola)
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Author: Sebastien Riou (acapola)
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Creation date: 17:16:40 01/09/2011
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Creation date: 17:16:40 01/09/2011
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$LastChangedDate: 2011-02-18 15:23:07 +0100 (Fri, 18 Feb 2011) $
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$LastChangedDate: 2011-03-07 14:17:52 +0100 (Mon, 07 Mar 2011) $
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$LastChangedBy: acapola $
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$LastChangedBy: acapola $
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$LastChangedRevision: 17 $
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$LastChangedRevision: 18 $
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$HeadURL: file:///svn/iso7816_3_master/iso7816_3_master/trunk/sources/Iso7816_3_Master.v $
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$HeadURL: file:///svn/iso7816_3_master/iso7816_3_master/trunk/sources/Iso7816_3_Master.v $
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This file is under the BSD licence:
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This file is under the BSD licence:
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Copyright (c) 2011, Sebastien Riou
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Copyright (c) 2011, Sebastien Riou
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output wire tsError,//high if TS character is wrong
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output wire tsError,//high if TS character is wrong
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output wire tsReceived,
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output wire tsReceived,
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output wire atrIsEarly,//high if TS received before 400 cycles after reset release
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output wire atrIsEarly,//high if TS received before 400 cycles after reset release
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output wire atrIsLate,//high if TS is still not received after 40000 cycles after reset release
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output wire atrIsLate,//high if TS is still not received after 40000 cycles after reset release
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//ISO7816 signals
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//ISO7816 signals
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inout wire isoSio,
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//inout wire isoSio,//not synthesisable on FPGA :-S
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output wire isTx,
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input wire isoSioIn,
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output wire isoSioOut,
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output wire isoClk,
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output wire isoClk,
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output reg isoReset,
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output reg isoReset,
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output reg isoVdd
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output reg isoVdd
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);
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);
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wire txRun,txPending, rxRun, rxStartBit, isTx, overrunErrorFlag, frameErrorFlag, bufferFull;
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wire txRun,txPending, rxRun, rxStartBit, overrunErrorFlag, frameErrorFlag, bufferFull;
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assign {txRun, txPending, rxRun, rxStartBit, isTx, overrunErrorFlag, frameErrorFlag, bufferFull} = statusOut;
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assign {txRun, txPending, rxRun, rxStartBit, isTx, overrunErrorFlag, frameErrorFlag, bufferFull} = statusOut;
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wire serialOut;
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//wire serialOut;
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assign isoSio = isTx ? serialOut : 1'bz;
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//not synthesisable on FPGA :-S
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pullup(isoSio);
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//assign isoSio = isTx ? serialOut : 1'bz;
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//pullup(isoSio);
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wire comClk;
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wire comClk;
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wire stopBit2=1'b1;//0: 1 stop bit, 1: 2 stop bits
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wire stopBit2=1'b1;//0: 1 stop bit, 1: 2 stop bits
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wire msbFirst = useIndirectConvention;//if 1, bits order is: startBit, b7, b6, b5...b0, parity
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wire msbFirst = useIndirectConvention;//if 1, bits order is: startBit, b7, b6, b5...b0, parity
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wire oddParity = 1'b0;//if 1, parity bit is such that data+parity have an odd number of 1
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wire oddParity = 1'b0;//if 1, parity bit is such that data+parity have an odd number of 1
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.msbFirst(msbFirst),
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.msbFirst(msbFirst),
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.dataOut(uart_dataOut),
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.dataOut(uart_dataOut),
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.nCsDataOut(nCsDataOut),
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.nCsDataOut(nCsDataOut),
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.statusOut(statusOut),
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.statusOut(statusOut),
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.nCsStatusOut(nCsStatusOut),
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.nCsStatusOut(nCsStatusOut),
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.serialIn(isoSio),
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.serialIn(isoSioIn),
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.serialOut(serialOut),
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.serialOut(isoSioOut),
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.comClk(comClk)
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.comClk(comClk)
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);
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);
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reg isoClkEn;
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reg isoClkEn;
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assign isoClk = isoClkEn ? comClk : 1'b0;
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assign isoClk = isoClkEn ? comClk : 1'b0;
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8'h3B: ts<=dataOut;
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8'h3B: ts<=dataOut;
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8'h03: ts<=8'h3F;//03 is 3F written LSB first and complemented
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8'h03: ts<=8'h3F;//03 is 3F written LSB first and complemented
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default: ts<=dataOut;
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default: ts<=dataOut;
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endcase
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endcase
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end
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end
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resetCnt<=resetCnt+1;
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resetCnt<=resetCnt+1'b1;
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end
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end
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if(startDeactivation) begin
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if(startDeactivation) begin
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isoVdd <= 1'b0;
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isoVdd <= 1'b0;
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isoClkEn <= 1'b0;
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isoClkEn <= 1'b0;
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isoReset <= 1'b0;
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isoReset <= 1'b0;
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isoClkEn <= 1'b1;
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isoClkEn <= 1'b1;
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if(16'h100 == resetCnt) begin
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if(16'h100 == resetCnt) begin
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isActivated <=1'b1;
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isActivated <=1'b1;
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isoReset <=1'b1;
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isoReset <=1'b1;
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end else
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end else
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resetCnt<=resetCnt + 1;
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resetCnt<=resetCnt + 1'b1;
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end else begin
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end else begin
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resetCnt<=16'b0;
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resetCnt<=16'b0;
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end
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end
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end
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end
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end
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end
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