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`timescale 1ns / 1ps
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`timescale 1ns / 1ps
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`default_nettype none
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//////////////////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Company:
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// Engineer:
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// Engineer:
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//
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//
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// Create Date: 17:16:40 01/09/2011
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// Create Date: 17:16:40 01/09/2011
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// Revision 0.01 - File Created
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// Revision 0.01 - File Created
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// Additional Comments:
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// Additional Comments:
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//
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//
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//////////////////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////////////////
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module Iso7816_3_Master(
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module Iso7816_3_Master(
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input nReset,
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input wire nReset,
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input clk,
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input wire clk,
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input [15:0] clkPerCycle,//not supported yet
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input wire [15:0] clkPerCycle,//not supported yet
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input startActivation,//Starts activation sequence
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input wire startActivation,//Starts activation sequence
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input startDeactivation,//Starts deactivation sequence
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input wire startDeactivation,//Starts deactivation sequence
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input [7:0] dataIn,
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input wire [7:0] dataIn,
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input nWeDataIn,
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input wire nWeDataIn,
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input [12:0] cyclePerEtu,
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input wire [12:0] cyclePerEtu,
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output [7:0] dataOut,
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output wire [7:0] dataOut,
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input nCsDataOut,
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input wire nCsDataOut,
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output [7:0] statusOut,
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output wire [7:0] statusOut,
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input nCsStatusOut,
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input wire nCsStatusOut,
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output reg isActivated,//set to high by activation sequence, set to low by deactivation sequence
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output reg isActivated,//set to high by activation sequence, set to low by deactivation sequence
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output useIndirectConvention,
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output wire useIndirectConvention,
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output tsError,//high if TS character is wrong
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output wire tsError,//high if TS character is wrong
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output tsReceived,
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output wire tsReceived,
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output atrIsEarly,//high if TS received before 400 cycles after reset release
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output wire atrIsEarly,//high if TS received before 400 cycles after reset release
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output atrIsLate,//high if TS is still not received after 40000 cycles after reset release
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output wire atrIsLate,//high if TS is still not received after 40000 cycles after reset release
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//ISO7816 signals
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//ISO7816 signals
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inout isoSio,
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inout wire isoSio,
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output isoClk,
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output wire isoClk,
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output reg isoReset,
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output reg isoReset,
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output reg isoVdd
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output reg isoVdd
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);
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);
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wire txRun,txPending, rxRun, rxStartBit, isTx, overrunErrorFlag, frameErrorFlag, bufferFull;
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wire txRun,txPending, rxRun, rxStartBit, isTx, overrunErrorFlag, frameErrorFlag, bufferFull;
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assign {txRun, txPending, rxRun, rxStartBit, isTx, overrunErrorFlag, frameErrorFlag, bufferFull} = statusOut;
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assign {txRun, txPending, rxRun, rxStartBit, isTx, overrunErrorFlag, frameErrorFlag, bufferFull} = statusOut;
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wire serialOut;
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assign isoSio = isTx ? serialOut : 1'bz;
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assign isoSio = isTx ? serialOut : 1'bz;
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pullup(isoSio);
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pullup(isoSio);
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wire comClk;
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wire comClk;
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HalfDuplexUartIf uart (
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HalfDuplexUartIf uart (
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