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/*
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/*
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Author: Sebastien Riou (acapola)
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Author: Sebastien Riou (acapola)
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Creation date: 23:57:02 08/31/2010
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Creation date: 23:57:02 08/31/2010
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$LastChangedDate: 2011-01-29 13:16:17 +0100 (Sat, 29 Jan 2011) $
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$LastChangedDate: 2011-02-14 15:11:43 +0100 (Mon, 14 Feb 2011) $
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$LastChangedBy: acapola $
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$LastChangedBy: acapola $
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$LastChangedRevision: 11 $
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$LastChangedRevision: 16 $
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$HeadURL: file:///svn/iso7816_3_master/iso7816_3_master/trunk/sources/RxCore.v $
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$HeadURL: file:///svn/iso7816_3_master/iso7816_3_master/trunk/sources/RxCore.v $
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This file is under the BSD licence:
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This file is under the BSD licence:
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Copyright (c) 2011, Sebastien Riou
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Copyright (c) 2011, Sebastien Riou
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SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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*/
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`default_nettype none
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`default_nettype none
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`timescale 1ns / 1ps
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`timescale 1ns / 1ps
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module RxCore(
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module RxCore
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#(//parameters to override
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parameter CLOCK_PER_BIT_WIDTH = 13, //allow to support default speed of ISO7816
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parameter PRECISE_STOP_BIT = 0, //if 1, stopBit signal goes high exactly at start of stop bit instead of middle of parity bit
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//default conventions (nothing to do with iso7816's convention, this is configured dynamically by the inputs)
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parameter START_BIT = 1'b0,
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parameter STOP_BIT1 = 1'b1,
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parameter STOP_BIT2 = 1'b1
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)
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(
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output reg [7:0] dataOut,
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output reg [7:0] dataOut,
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output reg overrunErrorFlag, //new data has been received before dataOut was read
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output reg overrunErrorFlag, //new data has been received before dataOut was read
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output reg dataOutReadyFlag, //new data available
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output reg dataOutReadyFlag, //new data available
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output reg frameErrorFlag, //bad parity or bad stop bits
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output reg frameErrorFlag, //bad parity or bad stop bits
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output reg endOfRx, //one cycle pulse: 1 during last cycle of last stop bit
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output reg endOfRx, //one cycle pulse: 1 during last cycle of last stop bit
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input wire bitClocksCounterEarlyMatch,
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input wire bitClocksCounterEarlyMatch,
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input wire bitClocksCounterMatch,
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input wire bitClocksCounterMatch,
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input wire [CLOCK_PER_BIT_WIDTH-1:0] bitClocksCounter
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input wire [CLOCK_PER_BIT_WIDTH-1:0] bitClocksCounter
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);
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);
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//parameters to override
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parameter CLOCK_PER_BIT_WIDTH = 13; //allow to support default speed of ISO7816
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parameter PRECISE_STOP_BIT = 0; //if 1, stopBit signal goes high exactly at start of stop bit instead of middle of parity bit
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//default conventions
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parameter START_BIT = 1'b0;
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parameter STOP_BIT1 = 1'b1;
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parameter STOP_BIT2 = 1'b1;
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//constant definition for states
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//constant definition for states
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localparam IDLE_STATE = 3'b000;
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localparam IDLE_STATE = 3'b000;
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localparam START_STATE = 3'b001;
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localparam START_STATE = 3'b001;
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localparam DATA_STATE = 3'b011;
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localparam DATA_STATE = 3'b011;
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localparam PARITY_STATE = 3'b010;
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localparam PARITY_STATE = 3'b010;
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